Neural Architectures TRIZ Cases

Partitioning neural networks into subgraphs assigns weights to dedicated accelerators, eliminating dynamic memory overhead and reducing latency.

A convolutional basis filter layer decomposes kernels into scaled components to reduce computational operations.

Complex clipping reduces linear dependencies in time-series data, resolving overparameterization and improving generalization.

A neural network pruner removes zero-weighted neurons to reduce model size.

A CMOS artificial neuron circuit uses a PMOS-NMOS bridge to integrate external excitation current.

A Ruler activation function processes capsule nodes through iterative affine transformations to generate sparse vector representations.

A self-converging generative network merges generator and discriminator functions into a single unified structure to produce high-fidelity images.

Distributing weight tensors across local core memories reduces memory access latency and improves energy efficiency in convolutional operations.

A scalable deep neural network accelerator uses activation sparsity removal blocks to process zero weights and activations within network processing units.

A generative probabilistic model extracts features via a backbone neural network and clusters them using negative log-likelihood minimization.

Compensating hardware threshold variations in spiking neural networks by adjusting effective thresholds to maintain inference accuracy.

A neurosynaptic system buffers axonal inputs and maps external signals through dedicated permutation units.

DAG path addressing organizes propositions into a generalization hierarchy using unique address ranges.

A modified transformer attention mechanism extracts significant scores to lower computational resource usage while maintaining classification accuracy.

A neural network alarm detector enters a user-instructed training mode to label disturbances as false or genuine signals.

A machine learning accelerator evaluates input and weight properties to selectively skip multiply-and-accumulate operations.

Neural networks generate optical system designs from training data, overcoming software limitations in structural modification.

A water pollution neural network calculates weighted Euclidean and clustering distances between sample data and output neuron weight vectors to identify sources.

A neural network training method fuses inter-class confusion and intra-class distance penalties into a single loss function for audio recognition.

Tile-based execution reduces external memory access by storing overlapping input tiles in buffer memory for continuous convolution operations.

A neural apparatus processes decoded signals using internal neuron dynamics to encode output signals for subsequent transmission.

Gradient ascent computes image perturbations to modify few-shot training samples, eliminating separate generator networks and reducing computational overhead.

A memristive accelerator partitions sparse weight matrices into zero-value and non-zero sub-blocks for efficient inference.

A neuron synapse bifunctional element combines spike generation and weight modulation in a single oxide semiconductor structure.

Crossbar arrays map neural weights through conductance states, resolving energy efficiency and scalability bottlenecks in machine learning hardware.

A balanced pruning method partitions deep neural network weights into groups to enforce uniform sparsity distribution across processing elements.

Profiling session-based recommendation model layers determines network bandwidth and layer performance to deploy optimal components across CPUs, GPUs, or FPGAs.

Intervention testing on neural networks distinguishes confounding events from causal ones, enabling accurate root cause analysis without inducing malfunctions.

A controller neural network automatically generates child architectures using reinforcement learning to identify optimal configurations.

Pre-computed statistics from training mini-batches normalize inference tensors, reducing data access frequency and accelerating neural network training.

Clustering-based codebook quantization compresses deep neural network weights while preserving model accuracy.

Branching neural network layers using output feature map entropy to select processing paths.

Segmented soma units simulate neural growth and learning by managing feature transfer and firing patterns to resolve complexity trade-offs.

Local inference at the radar ECU reduces computational workload on the central processor while maintaining detection accuracy.

A neural network processing unit executes tensor operations using configurable floating-point and fixed-point number representations.

A neural network division method splits layers into groups and operation chunks to minimize execution cycles on accelerators.

Tensor ring decomposition compresses neural network models, enabling faster inference and lower power consumption on resource-constrained devices.

Graph-based model detects loops in neural network computation graphs to reduce time and memory resources required for evaluation.

Binary neural networks identify test dependencies, reducing manual analysis time and improving developer productivity.

A neural network computation method adjusts convolution order based on feature map sizes to optimize data access patterns.

A dedicated pre-pooler executes pooling operations on tensor data before the multiply-add array processes it.

A ReLU-based activation function with configurable negative gradients paired with probability distribution weight initialization.

Entropy-based outlier detection identifies anomalous inputs in trained classifiers to mitigate adversarial attacks and improve security.

A neuromorphic architecture uses interconnected internal state information to modify neuron operations and strengthen input signals.

Segmenting parameter value distributions with breaking points allows independent quantization per section, reducing accuracy drop from uniform compression.

A template fuse unit merges adjacent neural network layers, reducing on chip and off chip data transfer overheads while maintaining computing capability.

A bidirectional data processing apparatus integrates storage and computing via a memristor array to perform inference and training tasks.