Conductive Layer Buried Substrate for Vertical Transistors
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing transistor sizes and driving voltage while increasing integration density, particularly in forming efficient silicon-on-insulator (SOI) substrates and optimizing vertical transistors for improved functional characteristics.
Innovation Solution
A conductive layer buried-type substrate is developed, featuring a silicon oxidation layer bonded to a supporting substrate with an adhesion promotion layer and a metal layer, along with a single crystal semiconductor layer, enabling the formation of vertical transistors and buried interconnection lines for enhanced semiconductor device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional SOI substrate is formed by wafer bonding without a conductive layer, then the substrate structure is simple, but the electrical characteristics and integration density are insufficient
Solution Approach 1:
The patent embeds a conductive layer within the substrate structure, nesting it between the silicon oxidation layer and the single crystal semiconductor layer. This nested configuration allows the conductive layer to be integrated without disrupting the overall substrate architecture, improving electrical characteristics while maintaining structural compactness
Solution Approach 2:
The patent introduces an adhesion promotion layer as an intermediary between the silicon oxidation layer and the conductive layer. This intermediary layer ensures strong bonding between the conductive layer and the substrate, preventing delamination and improving reliability without adding significant structural complexity
2Productivity
If transistor sizes are reduced to increase integration density, then the integration degree increases, but the manufacturing precision requirements become more stringent
Solution Approach 1:
The patent introduces a vertical dimension to the transistor structure by forming vertical transistors that extend through the substrate thickness. This dimensional change allows for higher integration density in the vertical direction, reducing the demand for lateral scaling and thereby easing manufacturing precision requirements
Solution Approach 2:
The patent divides the substrate into distinct functional layers including the silicon oxidation layer, adhesion promotion layer, conductive layer, and single crystal semiconductor layer. This segmentation allows each layer to be optimized independently, improving manufacturability while achieving high integration density
3Reliability
If driving voltage is reduced to improve device performance, then the device efficiency increases, but the adhesion between layers becomes insufficient
Solution Approach 1:
The patent introduces an adhesion promotion layer as an intermediary between the silicon oxidation layer and the conductive layer. This intermediary layer ensures strong bonding between the conductive layer and the substrate, preventing delamination and improving reliability without adding significant structural complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the creation of high-integration, low-resistance semiconductor devices with improved electrical characteristics and reliability, facilitating the development of advanced memory and logic circuits.
Implementation Method 1
an adhesion promotion layer that is formed on the silicon oxidation layer and improves an adhesion between the silicon oxidation layer and a conductive layer
Implementation Method 2
a silicon oxidation layer bonded to a supporting substrate
Data Source
AI summary
A conductive layer buried-type substrate is disclosed. The substrate includes a silicon oxidation layer bonded to a supporting substrate, an adhesion promotion layer that is formed on the silicon oxidation layer and improves an adhesion between the silicon oxidation layer and a conductive layer, wherein the conductive layer is formed on the adhesion promotion layer and comprises a metal layer, and a single crystal semiconductor layer formed on the conductive layer.