Conductive Interconnection Structure With Self-Aligned Via Patterning
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Solution Overview
Problem
The increasing complexity of semiconductor device manufacturing due to shrinking feature sizes poses challenges in forming reliable connections and interconnects, particularly with materials like ruthenium, which face yield and cost issues as sizes shrink.
Innovation Solution
A method involving a self-aligned via (SAV) patterning process is employed, where a trench filling portion is formed before hard mask deposition, ensuring precise via definition and reducing via contact resistance by increasing contact area, preventing via misalignment and via-induced-metal-bridge (VIMB) through precise lithography overlay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If feature sizes continue to decrease to improve IC generation and circuit density, then more complex circuits and smaller devices are achieved, but manufacturing complexity and processing difficulty increase significantly
Solution Approach 1:
The patent applies preliminary action by forming a mandrel structure and trench filling portion before via definition. This self-aligned via (SAV) patterning process pre-establishes reference structures that guide subsequent via formation, eliminating the need for separate alignment steps and reducing manufacturing complexity despite smaller feature sizes
Solution Approach 2:
The patent introduces a trench filling portion as an intermediary structure between the mandrel and the final via. This intermediary element serves as a self-aligned mask and reference feature, enabling precise via placement without complex alignment procedures, thus reducing processing difficulty while maintaining small feature sizes
2Length of moving object
If conventional via patterning is used with shrinking feature sizes, then smaller vias are formed, but via misalignment and via-induced-metal-bridge (VIMB) defects increase
Solution Approach 1:
The patent implements self-service through self-aligned via patterning where the trench filling portion automatically serves as the alignment reference for via formation. The via is defined by etching through the trench filling portion, ensuring automatic self-alignment with the underlying mandrel structure, thereby eliminating misalignment defects and VIMB while forming smaller vias
Solution Approach 2:
The trench filling portion is formed in advance as a self-aligned reference structure before via definition. This preliminary structure provides precise geometric constraints that guide via placement, ensuring sub-10nm alignment accuracy and preventing via-induced-metal-bridge defects in scaled devices
3Area of moving object
If via contact area is reduced with smaller feature sizes, then higher circuit density is achieved, but via contact resistance increases
Solution Approach 1:
The patent applies local quality by creating a via structure with enlarged contact footprint at the metal-dielectric interface through self-aligned via patterning. The via maintains a larger effective contact area at critical interfaces while keeping the overall via dimensions small, thereby reducing via contact resistance without compromising circuit density
Solution Approach 2:
The patent addresses via contact resistance by transitioning from a single-dimension via size reduction to a multi-dimensional approach. The via contact area is optimized in the lateral dimension through self-aligned patterning while maintaining appropriate depth, creating an optimized contact geometry that reduces resistance without increasing overall via size and preserves circuit density
Data Source
AI summary
A conductive interconnection structure includes a conductive feature part, a dielectric structure, a trench filling portion, a via portion and a metal layer. The dielectric structure is formed over the conductive feature part. The dielectric structure includes a first dielectric layer and a second dielectric layer stacked on each other. The second dielectric layer covers the first dielectric layer. The trench filling portion is embedded in the dielectric structure, and the trench filling portion and the second dielectric layer have different etching selectivities. The via portion is located in the first dielectric layer at the bottom surface of the trench filling portion. The metal layer penetrates the dielectric structure, the trench filling portion and the via portion, and the bottom surface of the metal layer is electrically connected to the conductive feature part.