Conductive Pillar Structure for Stress-Resistant Chip Bonding
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Solution Overview
Problem
The challenge of forming reliable semiconductor devices at smaller sizes due to the increasing complexity and difficulty of fabrication processes in the semiconductor integrated circuit (IC) industry, where feature sizes continue to decrease.
Innovation Solution
A semiconductor device structure is developed with a conductive pillar and conductive lines that include a thick top metal wiring layer, conductive via structure, and a thick wiring layer, which are formed using specific deposition and etching processes to enhance alignment tolerance and reduce stress migration, and are bonded to a wiring substrate using a solder bump.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency and cost are improved, but fabrication process complexity and difficulty increase
Solution Approach 1:
The patent segments the interconnect structure into multiple distinct layers including thick top metal wiring layers, thick bottom metal wiring layers, and conductive via structures. This segmentation allows each layer to be optimized independently for its specific function, enabling reliable fabrication at smaller feature sizes while maintaining production efficiency
Solution Approach 2:
The patent transitions from planar interconnect structures to three-dimensional structures with thick top and bottom metal wiring layers extending in multiple dimensions. This dimensional change provides additional routing space and reduces congestion, simplifying the fabrication process while maintaining high functional density
2Productivity
If feature sizes continue to decrease, then functional density increases, but manufacturing reliability decreases
Solution Approach 1:
The patent changes the dimensional parameters of the interconnect structure by implementing thick top metal wiring layers and thick bottom metal wiring layers with controlled thicknesses. This parameter optimization ensures reliable electrical connections and stress distribution, maintaining manufacturing reliability while enabling smaller feature sizes and higher functional density
Solution Approach 2:
The patent employs composite interconnect structures combining multiple materials including thick top metal wiring layers, thick bottom metal wiring layers, and conductive via structures with different material compositions. This composite approach optimizes electrical performance and mechanical reliability, ensuring consistent manufacturing quality at reduced feature sizes
Data Source
AI summary
A semiconductor device structure is provided. The semiconductor device structure includes a conductive feature over a substrate and an insulating layer over the conductive feature. The semiconductor device structure also includes a conductive pillar over the conductive feature and the insulating layer. The conductive pillar has a protruding connecting portion and a protruding locking portion. The protruding connecting portion extends from a lower surface of the conductive pillar towards the conductive feature and is electrically connected to the conductive feature. The protruding locking portion extends from the lower surface of the conductive pillar towards the substrate and extends into the insulating layer. The protruding connecting portion is closer to the substrate than the protruding locking portion. A bottom of the protruding locking portion is wider than a bottom of the protruding connecting portion.