Conductive Plate Slit Layout for Stable Semiconductor Bonding

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The existing semiconductor devices face reliability issues due to changes in current path inductance caused by slits in the conductive plate, which affect the electrical properties and lead to positional shifts of semiconductor chips and wiring terminals during solder bonding.

Innovation Solution

A semiconductor device design featuring a conductive plate with specific slit configurations, including a continuous penetrating slit between chip areas and non-penetrating continuous or broken line slits between chip and terminal areas, to control solder spread and prevent positional shifts while maintaining low inductance wiring.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If slits are formed in the conductive plate to control solder spread and prevent positional shifts, then manufacturing precision is improved, but inductance changes occur affecting reliability

Engineering Contradiction:
Improvepositional accuracy of semiconductor chips and wiring terminalsVSAvoidelectrical property stability
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The conductive plate is designed with differentiated slit configurations: a first slit (continuous, penetrating) in the first chip area for precise solder control, and second/third slits (non-penetrating or broken line) in the terminal area to minimize inductance impact. This local differentiation allows each region to optimize for its specific function while balancing manufacturing precision and electrical reliability.

Inventive Principle:
Principle #3Local quality

2Manufacturing precision

If continuous penetrating slits are used to control solder spread, then manufacturing precision is improved, but inductance increases reducing reliability

Engineering Contradiction:
Improvesolder spread controlVSAvoidcurrent path inductance
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The conductive plate is segmented into distinct functional areas (first chip area and terminal area) with different slit configurations. The first slit penetrates continuously to control solder spread in the chip bonding area, while the second and third slits are non-penetrating or broken line patterns in the terminal area to maintain low inductance for current paths.

Inventive Principle:
Principle #1Segmentation

3Manufacturing precision

If slits are formed around bonding areas to prevent solder displacement, then manufacturing precision is improved, but device complexity increases

Engineering Contradiction:
Improvebonding area controlVSAvoidconductive plate structure
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

Rather than uniformly complexifying the entire conductive plate, the invention applies local quality by implementing different slit patterns in different regions: simple continuous penetrating slits where needed for solder control, and simpler non-penetrating or broken line slits in areas where inductance must be minimized, thereby controlling complexity locally rather than globally.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The design effectively prevents solder spread and positional shifts, enhancing the reliability and electrical properties of the semiconductor device by maintaining controlled solder thickness and preventing inductance changes.

Implementation Method 1

the first slit is provided as one continuous slit that penetrates completely through the conductive plate in a thickness direction orthogonal to direction of the front surface of the conductive plate and reaches the insulating plate

Methodology Applied
Scientific EffectPhysical barrier effect:

Implementation Method 2

one of the second slit and the third slit is provided as either one continuous slit that does not penetrate through the conductive plate in the thickness direction or a plurality of slits forming a broken line pattern, each of the plurality of slits penetrating completely through the conductive plate in the thickness direction and reaching the insulating plate

Methodology Applied
Scientific EffectPartial barrier effect:

Data Source

PatentUS12009310B2Semiconductor device
Publication Date: 2024.06.11 FUJI ELECTRIC CO LTD
  • US12009310B2 patent drawing
  • US12009310B2 patent drawing
  • US12009310B2 patent drawing

AI summary

A conductive plate includes a first slit formed in the space between a first chip area and a second chip area, a second slit formed in the space between the first chip area and a terminal area, and a third slit formed in the space between the second chip area and the terminal area. The first slit is a continuous line that penetrates through the conductive plate, whereas the second and third slits are continuous lines that do not penetrate through the conductive plate.