Conductive Through-Polymer Vias for Integrated Capacitive Structures
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Solution Overview
Problem
Existing semiconductor devices face challenges in integrating high-capacitance capacitors with minimal footprint and thermal stability, particularly in power supply systems where parasitic effects and thermal expansion mismatches lead to device failures.
Innovation Solution
The integration of high-density nanometer-sized three-dimensional capacitors within semiconductor packages using conductive through-polymer vias, which form polymeric bonds with metals and insulators, allowing for concurrent fabrication and connection to chip circuitry, reducing thermal expansion mismatches and enabling compact, reliable designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional discrete capacitors are used in power supply systems, then ease of manufacture is maintained, but device footprint and parasitic effects increase
Solution Approach 1:
The patent merges the capacitor structure with the semiconductor package by integrating high-density capacitive elements directly into the package substrate. This integration combines previously separate components (capacitor and package) into a unified structure, reducing overall footprint while maintaining manufacturing feasibility through standardized integration processes
Solution Approach 2:
The patent transitions from planar capacitor layouts to three-dimensional stacked capacitor structures. By utilizing vertical stacking and multi-layer configurations, the capacitor achieves higher capacitance density within a reduced footprint, effectively adding the third dimension to the traditional two-dimensional layout
2Area of stationary object
If capacitor size is reduced to minimize footprint, then area is improved, but capacitance value and thermal stability deteriorate
Solution Approach 1:
The patent employs composite material structures for the capacitor, combining multiple dielectric layers with different thermal expansion coefficients and capacitance characteristics. This composite approach allows the small capacitor to achieve both high capacitance density and improved thermal stability by selecting materials that compensate for each other's weaknesses under thermal stress
Solution Approach 2:
The patent implements nested capacitor structures where multiple capacitive elements are stacked vertically within a compact footprint. This nesting approach allows smaller individual capacitors to achieve higher total capacitance while maintaining thermal stability through distributed thermal pathways and balanced material composition across layers
3Manufacturing precision
If through-silicon vias are used for conducting signals, then manufacturing precision is improved, but thermal expansion mismatch causes delamination and device failure
Solution Approach 1:
The patent introduces an intermediary compliant layer between the rigid silicon substrate and the overlying capacitor structures. This compliant layer acts as a buffer that absorbs thermal expansion mismatches during temperature cycling, preventing stress concentration and delamination while allowing precise via alignment to be maintained through the intermediary's flexibility
Solution Approach 2:
The patent modifies the mechanical and thermal parameters of the via structure by using alternative via materials or composite via structures with matched thermal expansion coefficients. This parameter change allows the via to maintain manufacturing precision while accommodating thermal cycling without causing delamination or device failure
4Area of stationary object
If capacitors are placed in tight proximity to other components, then board space is conserved, but parasitic electrical effects increase
Solution Approach 1:
The patent applies local quality optimization by designing the integrated capacitor with non-uniform electrode and dielectric distributions. This allows the capacitor to achieve high capacitance density in specific local regions while maintaining electrical isolation and minimizing parasitic coupling with adjacent components through strategically placed shielding structures and optimized trace routing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in compact semiconductor devices with high capacitance density, stable frequency performance, and enhanced reliability across temperature variations, reducing electrical parasitics and allowing increased switching frequencies, thus shrinking the size of bulky inductors.
Implementation Method 1
The methodology accepts pre-fabricated sheets of high density nano-capacitors, attaches the sheets to semiconductor wafers, fabricates the interconnections between capacitors and chip circuitry at various levels of a multi-level laminate
Implementation Method 2
The conductive through-polymer vias of the invention are distinguished by the absence of a problem of mismatched coefficients of thermal expansion (which is known to plague through-silicon-vias), avoiding device failures due to delamination and temperature cycling
Data Source
AI summary
An electronic system comprising an electronic body (301) with terminal pads (310) and at least one capacitor embedded in the electronic body. The capacitor including an insulating and adhesive first polymeric film (302) covering the body surface except the terminal pads; a sheet (320) of high-density capacitive elements, the first capacitor terminal being a metal foil (321) attached to film (302), the second terminal a conductive polymeric compound (324), and the insulator a dielectric skin (323). Sheet (320) has sets of via holes: the first set holes reaching metal foil 321), the second set holes reaching the terminals (310), and the third set holes reaching the conductive polymeric compound (324). An insulating second polymeric film (303) lining the sidewalls of the holes and planarizing the sheet surface; and metal (432) filling the via holes between the polymeric sidewalls and forming conductive traces and attachment pads on the system surface.