Conductive Posts Replace TSVs for 3D Package Fabrication
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Solution Overview
Problem
Conventional 3D chip stacking technologies face challenges in achieving a suitable depth-to-width ratio for through silicon vias (TSVs), leading to high fabrication costs, limited product yield, and potential bridging or leakage issues due to copper ion diffusion, as well as difficulties in achieving high pin counts and miniaturization.
Innovation Solution
The use of conductive posts with a reduced length-to-width ratio, fabricated on a substrate with a thin temporary carrier and encapsulant, replaces traditional TSVs, allowing for improved miniaturization, reduced fabrication costs, and increased product yield by eliminating the need for complex etching processes and minimizing copper ion diffusion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional through silicon vias (TSVs) are used with high depth-to-width ratio, then electrical connection is achieved, but fabrication cost increases and product yield decreases
Solution Approach 1:
The patent changes the depth-to-width ratio parameter of the conductive structure from traditional high ratio (100μm depth/10μm width) to reduced ratio (50μm depth/10μm width), thereby reducing fabrication difficulty and increasing product yield while maintaining electrical connection functionality
Solution Approach 2:
The patent extracts the conductive posts from the substrate after encapsulation, removing them from their original positions to create through-holes that provide electrical connections, thereby avoiding the need to maintain high depth-to-width ratio throughout the entire fabrication process
2Length of stationary object
If mechanical grinding and CMP processes are used to reduce substrate thickness, then TSV exposure is achieved, but total thickness variation increases and substrate cracking occurs
Solution Approach 1:
The patent performs encapsulation before substrate thinning, creating a protective layer that compensates for thickness variations and prevents cracking during subsequent grinding and CMP processes, thereby maintaining manufacturing precision
Solution Approach 2:
The encapsulant layer acts as a cushioning layer that absorbs stress and compensates for thickness variations, preventing substrate cracking during mechanical grinding and CMP processes
3Ease of manufacture
If wet etching process is used to remove substrate, then TSV exposure is achieved, but fabrication time increases and chemical agent consumption increases
Solution Approach 1:
The patent extracts conductive posts from the substrate after encapsulation to create through-holes, eliminating the need for time-consuming wet etching processes while achieving the same TSV exposure result
Solution Approach 2:
The patent replaces the chemical wet etching process with a mechanical extraction process, where conductive posts are removed physically after encapsulation, thereby reducing fabrication time and chemical agent consumption
4Reliability
If copper-filled TSVs are formed, then electrical connection is achieved, but copper ion diffusion causes bridging or leakage issues
Solution Approach 1:
The patent extracts conductive posts after encapsulation, creating through-holes that eliminate the copper-filled TSV structure and thereby prevent copper ion diffusion and associated bridging or leakage issues
Solution Approach 2:
The patent converts the potential harm of copper ion diffusion by removing the copper-filled structure entirely, using the extracted through-holes as the electrical connection path instead, thereby eliminating the source of copper ion contamination
Data Source
AI summary
A substrate structure is provided, which includes: a substrate body having a first surface and a second surface opposite to the first surface; and a plurality of conductive posts disposed on the first surface of the substrate body and electrically connected to the substrate body. By replacing conventional through silicon vias (TSVs) with the conductive posts, the present disclosure greatly reduces the fabrication cost. The present disclosure further provides an electronic package having the substrate structure and a method for fabricating the electronic package.