Conductive Silicon Deposition for Memory Array Electrical Coupling
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Solution Overview
Problem
Current memory array fabrication methods face challenges in efficiently forming strings of memory cells with optimal electrical coupling and structural integrity, particularly in achieving consistent and reliable conductivity across crystalline silicon grains, which affects the performance and reliability of memory cells.
Innovation Solution
The method involves forming a conductor tier with laterally-spaced memory-block regions comprising alternating insulative and conductive tiers, creating channel-material strings that extend through these tiers, and selectively depositing conductively-doped silicon to electrically couple the channel material to the conductor tier, ensuring a significant increase in the average maximum-straight-line distance across crystal grains of the deposited silicon, thereby enhancing electrical conductivity and structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fabrication methods are used to form memory cell strings, then the manufacturing process is simpler, but the electrical coupling and structural integrity are insufficient
Solution Approach 1:
The method performs preliminary actions by forming sacrificial tiers and channel-material strings before finalizing the memory cell structure. The sacrificial tiers are deposited and patterned first, followed by channel-material string formation, then the sacrificial tiers are removed to create void spaces. This preliminary structuring enables subsequent selective silicon deposition to achieve optimal electrical coupling and structural integrity before the actual memory cell operation.
Solution Approach 2:
The patent uses conductively-doped silicon as an intermediary material that is selectively deposited into void spaces to electrically couple channel-material strings to conductor tiers. This intermediary silicon layer acts as a mediator that bridges the electrical connection between the channel material and conductor tiers, ensuring optimal electrical coupling and structural integrity without requiring direct contact between the channel material and conductor tiers.
2Reliability
If standard deposition methods are used, then the manufacturing process is faster, but the conductivity consistency across crystal grains is poor
Solution Approach 1:
The patent applies local quality by selectively depositing conductively-doped silicon only in specific void spaces where electrical coupling is needed, rather than uniformly depositing material across the entire substrate. The selective deposition process targets specific locations between channel-material strings and conductor tiers, ensuring optimal conductivity consistency in critical areas while maintaining manufacturing efficiency.
Solution Approach 2:
The method changes deposition parameters by controlling the silicon deposition process to achieve specific crystal grain characteristics. The deposited silicon is engineered to have an average maximum-straight-line distance across crystal grains that is at least 20% greater than the channel material, which optimizes electrical conductivity and consistency across the memory cell structure.
3Reliability
If smaller crystal grain distance is used, then the deposition process is simpler, but the electrical conductivity and structural integrity are reduced
Solution Approach 1:
The patent explicitly changes the crystal grain distance parameter by specifying that the deposited silicon must have an average maximum-straight-line distance across crystal grains that is at least 20% greater than the channel material. This parameter change optimizes electrical conductivity and structural integrity while the selective deposition process controls the precise placement and dimensions of the silicon regions to achieve the desired crystal grain characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in improved electrical coupling and structural integrity of memory cells, leading to enhanced performance and reliability by ensuring consistent conductivity and reduced pinching-off issues at trenches, thus improving the overall efficiency of the memory array.
Implementation Method 1
conductively-doped silicon is selectively deposited onto and from the exposed silicon-containing surface
Data Source
AI summary
A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. Laterally-spaced memory-block regions individually comprising a vertical stack comprising alternating first tiers and second tiers are formed directly above the conductor tier. Channel-material strings extend through the first tiers and the second tiers. A void space is formed directly above the conductor tier laterally-across individual of the memory-block regions. The void space comprises an exposed silicon-containing surface. Conductively-doped silicon is selectively deposited onto and from the exposed silicon-containing surface. The conductively-doped silicon is directly electrically coupled to the channel material of the channel-material strings and is directly electrically coupled to the conductor material of the conductor tier and directly electrically couples the channel-material strings to the conductor material of the conductor tier. Other embodiments, including structure independent of method, are disclosed.