Conductive Crossovers for Planar Hermetic Vacuum Packaging
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Solution Overview
Problem
Hermetic sealing of MEMS devices with non-planar topography due to patterned conductive traces is challenging, leading to degraded seals and increased production costs due to the need for additional material and planarization processes.
Innovation Solution
Creating conductive crossovers in a planar seal area by modifying the semiconductor layer's composition without changing its topography, using doping or silicide formation, and bonding planar semiconductor layers without planarization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If patterned conductive traces are created by removing material between adjacent traces, then conductive crossovers can be formed, but the surface topography becomes non-planar which degrades hermetic seal quality
Solution Approach 1:
The patent extracts the harmful non-planar topography by removing material between adjacent conductive traces. This extraction of excess material creates a planar surface that enables high-quality hermetic sealing while maintaining the conductive crossover functionality through the remaining trace structures.
Solution Approach 2:
The patent changes the surface topography parameter from non-planar to planar through material removal. This parameter change in surface flatness directly improves hermetic seal quality while the conductive traces maintain their electrical functionality, resolving the contradiction between crossover formation and seal quality.
2Reliability
If additional material is added between adjacent traces to create planar topography, then hermetic seal quality improves, but production cost increases and additional planarization processing is required
Solution Approach 1:
Instead of adding material to create planarity (the conventional approach), the patent inverts the approach by removing material to achieve planarity. This inversion eliminates the need for additional planarization processing steps and reduces production costs while still achieving the desired planar surface for hermetic sealing.
Solution Approach 2:
The patent discards the additional material that would normally be added for planarization. By removing material between traces instead of adding material, the process recovers simplicity and reduces production costs while achieving the necessary planar surface quality for reliable hermetic sealing.
3Manufacturing precision
If CMP planarization is performed on large area semiconductor layers, then planar surface quality improves for bonding, but the process becomes costly and may become impossible as area increases
Solution Approach 1:
The patent performs preliminary material removal between conductive traces to create planar surfaces before bonding. This preliminary action achieves the necessary planarity without requiring subsequent CMP processing on large areas, making the process feasible and cost-effective for large-area semiconductor layers while maintaining high bonding quality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method maintains seal integrity and reduces production costs by eliminating the need for additional material and planarization steps, ensuring effective vacuum packaging and device performance.
Implementation Method 1
creating the conductive regions in the semiconductor layer comprises doping regions of the semiconductor layer to create conductive regions
Implementation Method 2
creating the conductive regions in the semiconductor layer comprises forming a silicide in regions of the semiconductor layer to create conductive regions
Implementation Method 3
MEMS devices may operate in a vacuum. For example, a bolometer array may operate in a vacuum to ensure longevity and accuracy of the device
Data Source
Figure 1A~1B
Figure 2A~2B
Figure 2C~2D
AI summary
In some embodiments, electromechanical systems including a semiconductor layer that has a planar surface and includes conductive and adjacent non-conductive regions and a hermetic seal applied above the planar surface and methods of manufacturing the systems are disclosed. In some embodiments, electromechanical devices that include first and second planar semiconductor layers are disclosed. Each of the semiconductor layers includes conductive regions, and at least one conductive region from each of the layers is electrically coupled to each other. Methods of manufacturing the electromechanical devices are also disclosed.