Conductive Via Buffer Layer for Plasma Charge Dissipation
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Solution Overview
Problem
Current methods for fabricating semiconductor devices with through electrodes, such as TSVs, face challenges in efficiently electrically connecting the electrodes to the substrate while preventing plasma charge accumulation, which can lead to electrical breakdown and production yield reduction.
Innovation Solution
The method involves forming a conductive via that penetrates through the substrate, with electrical grounding during plasma etching and the use of insulating and barrier layers to prevent plasma charge accumulation, and a buffer layer to facilitate etching and isolation, allowing for effective electrical connection and void detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the conductive via is electrically connected to the substrate during plasma etching, then plasma charge accumulation is prevented, but the complexity of the fabrication process increases due to additional grounding requirements
Solution Approach 1:
The method establishes electrical grounding between the substrate and conductive via before plasma etching begins. This preliminary action ensures that plasma charges have a discharge path from the start of the etching process, preventing charge accumulation that would otherwise occur during the etching operation.
Solution Approach 2:
The insulating layer with a controlled gap serves as an intermediary structure that enables electrical grounding while maintaining physical separation. The gap in the insulating layer provides a conductive path for plasma charge dissipation, acting as a mediator between the substrate and conductive via.
2Reliability
If the conductive via is completely isolated from the substrate by insulating layer, then electrical breakdown is prevented, but plasma charge accumulation occurs leading to production yield reduction
Solution Approach 1:
The insulating layer is designed with non-uniform properties: it provides complete insulation in most regions to prevent electrical breakdown, but contains a localized gap region that permits electrical grounding for plasma charge dissipation. This local quality variation allows simultaneous achievement of both insulation and charge management.
Solution Approach 2:
The insulating layer is segmented into insulating regions and a conductive gap region. This segmentation allows the structure to perform dual functions: blocking electrical breakdown paths while providing a discharge path for plasma charges during fabrication.
3Ease of manufacture
If the conductive via is formed with tapered portion, then etching process is facilitated, but the precision of electrical connection control becomes more difficult
Solution Approach 1:
The conductive via structure incorporates a tapered portion with specific geometric characteristics that facilitate etching, while the insulating layer gap is precisely controlled in location and dimension to maintain manufacturing precision for electrical connection control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the production yield by preventing plasma charge accumulation and enabling early detection of voids in the conductive via, ensuring good electrical characteristics and reliable semiconductor device fabrication.
Implementation Method 1
plasma etching a layer located over the first surface for connection to the conductive via through the layer
Implementation Method 2
The substrate and conductive via may be electrically grounded during the plasma etching
Implementation Method 3
The conductive via may be electrically isolated from the substrate by the insulating layer after the removing of the opposite second surface of the substrate
Implementation Method 4
plasma etching the second insulating layer to expose at least a portion of the conductive layer while the conductive via is electrically connected to the substrate through the gap in the first insulating layer
Data Source
AI summary
A semiconductor device includes a semiconductor substrate, a circuit layer including an interlayer insulating layer on an upper surface of the substrate, and a conductive via penetrating through the interlayer insulating layer and the substrate, and electrically connected to the circuit layer. The device further includes an insulating layer surrounding the conductive via, and located between the conductive via and the substrate and between the conductive via and interlayer insulating layer, and a buffer layer located between the insulating layer and the conductive via, and overlapping at least a portion of the interlayer insulating layer in a depth direction of the conductive via.