Configurable Bandwidth Memory Devices Using Stacked-Die Architecture
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Solution Overview
Problem
Current semiconductor memory subsystems face a mismatch in performance with modern host processors, leading to inefficiencies such as high idle times and a compromise between memory bandwidth and density, with existing JEDEC interface standards like DDR SDRAM being inadequate for future memory demands and lacking in power optimization.
Innovation Solution
The implementation of a stacked-die 3D memory architecture with shared control logic and memory vaults that enable concurrent data transfer, a standardized host processor interface, and configurable communication links to enhance memory system density, bandwidth, and scalability, while reducing re-design cycles as memory technology evolves.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If higher bandwidth memory interfaces are implemented, then memory bandwidth is improved, but the number of memory cards or modules that can be connected is limited due to JEDEC electrical specifications
Solution Approach 1:
The memory system is divided into multiple independent memory cards, each with its own memory controller. This segmentation allows each card to operate independently within JEDEC specifications while the aggregate system achieves higher total bandwidth through parallel operation of multiple cards.
Solution Approach 2:
The memory interface is designed to support multiple memory cards with standardized controllers that can handle various memory types and configurations. This universal interface design allows the system to scale from single-card to multi-card configurations without requiring redesign, maintaining adaptability while achieving high bandwidth through parallelism.
2Quantity of substance
If memory density is increased, then storage capacity is improved, but performance may be compromised due to electrical specification limits
Solution Approach 1:
The patent transitions from planar 2D memory expansion to 3D stacked memory architecture. Multiple memory dies are stacked vertically with interconnect layers between them, enabling significant density increases without increasing the footprint or violating electrical specifications, as each die operates independently at standard performance levels.
Solution Approach 2:
Multiple memory dies are combined into a single stacked memory module, merging their individual capacities to achieve high density. The memory controllers manage these combined resources, ensuring that performance is maintained through parallel access to multiple dies while achieving superior density compared to traditional planar arrangements.
3Productivity
If memory technology evolves to meet future bandwidth and density demands, then performance and density are improved, but interface redesign may be required
Solution Approach 1:
A universal memory interface architecture is implemented that can accommodate evolving memory technologies and performance requirements without requiring fundamental redesign. The standardized interface and controller design allow future memory dies with higher bandwidth capabilities to be integrated into the existing stacked memory framework, enabling technology evolution while maintaining interface consistency.
4Productivity
If more memory banks are powered on to increase bandwidth, then memory bandwidth is improved, but energy consumption increases
Solution Approach 1:
The memory system implements dynamic power management where the number of active memory banks is adjusted based on current workload demands. The memory controllers can selectively power on only the necessary number of memory banks required to handle the current traffic load, and scale down power consumption during low-demand periods, thereby achieving high bandwidth when needed while optimizing energy efficiency.
Data Source
AI summary
Memory devices and methods are described, such as those that include a stack of memory dies and an attached logic die. Method and devices described provide for configuring bandwidth for selected portions of a stack of memory dies. Additional devices, systems, and methods are disclosed.