Configurable Circuit Programmable Bus Area Reduction
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Solution Overview
Problem
Configurable circuits, such as FPGAs, face challenges in reducing overall circuit area due to the large number of wires and buffers required for high-speed signal transmission, despite the introduction of memory-type low resistance switch elements which do not sufficiently minimize the area.
Innovation Solution
The implementation of a configurable circuit with a programmable bus comprising short distance wires, direct wire connection switches, and programmable switches with buffers, allowing for efficient signal transmission by reducing the number of wires and buffers, and utilizing memory-type low resistance switch elements to minimize area occupancy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple kinds of wires (short distance and long distance) are prepared for high-speed signal transmission, then signal transmission speed is improved, but the number of wires increases and circuit area increases
Solution Approach 1:
The patent implements dynamic wire configuration where the same physical wire can be dynamically assigned as either short distance wire or long distance wire based on configuration data. This is achieved through programmable switches that can connect wires to different destinations, allowing the wire function to change dynamically rather than being fixed. This resolves the contradiction by eliminating the need for multiple dedicated wire types while maintaining high-speed transmission capabilities.
Solution Approach 2:
The patent makes wires multi-functional by enabling them to serve different purposes (short distance or long distance transmission) based on configuration. The same wire infrastructure can be reconfigured for different transmission ranges, making the wire system universal rather than requiring separate dedicated wires for each function. This reduces the total number of wires needed while maintaining performance.
2Adaptability or versatility
If the number of programmable switches is increased to match the number of wires, then wire connectivity is improved, but the area occupied by switches increases
Solution Approach 1:
The patent merges the functions of multiple switches into fewer switches by implementing a shared switch architecture. Instead of having dedicated switches for each wire, the system uses a pool of programmable switches that can be dynamically assigned to control different wire connections. This consolidation reduces the total number of switches while maintaining full connectivity capability.
Solution Approach 2:
The patent employs dynamic switch assignment where the same programmable switch can be reconfigured to control different wire connections at different times. This dynamic reuse of switch resources allows the system to maintain high adaptability and connectivity with fewer physical switches, reducing the area occupied by switch components.
3Power
If tristate buffers in programmable switches are designed with large driving force for long distance wires, then signal transmission capability is improved, but the area occupied by buffers increases
Solution Approach 1:
The patent merges buffer resources into a shared pool that serves multiple wires dynamically. Instead of having dedicated large buffers for each long distance wire, the system uses a smaller number of programmable buffers that can be assigned to different wires as needed. This consolidation reduces the total buffer area while maintaining sufficient driving force for long distance transmission when required.
Solution Approach 2:
The patent implements dynamic buffer assignment where buffers can be reconfigured to serve different wires based on the current transmission requirements. When long distance transmission is needed, buffers are assigned to provide large driving force; when short distance transmission suffices, buffers are reassigned or not used. This dynamic allocation maintains high power capability when needed while reducing average buffer area requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the overall circuit area by optimizing wire and buffer usage, enabling high-speed signal transmission with improved performance and reduced area occupancy compared to traditional configurations.
Implementation Method 1
a switch element (hereinafter, referred to as Memory-type low resistance switch element) was developed which can programmably set a high resistance state and a low resistance state
Data Source
AI summary
A configurable circuit of the present invention includes a plurality of logic blocks (4), and a programmable bus which can program connections of plurality of logic blocks (4). The programmable bus includes a plurality of wires (11—x) arranged for each of signal transmission ranges corresponding to plurality of logic blocks (4), direct wire connection switch (711—x) which can program whether to directly connect or disconnect the wires between the adjacent signal transmission ranges, input selector (30—x) which can program a connection with any one of the plurality of wires, and programmable switch (40—x) which can program whether to make a connection with the wire corresponding to the adjacent signal transmission range for each of the plurality of wires. A plurality of programmable switches (40—x) are arranged for at least one of plurality of logic blocks (4).


