Configurable Computing Array for Efficient Math Function Hardware Implementation
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Solution Overview
Problem
Conventional processors face challenges in hardware implementation of complex math functions due to limited resources, leading to slow and inefficient software computing for non-arithmetic functions, and existing configurable gate arrays are limited by fixed computing elements that cannot be reconfigured for math functions.
Innovation Solution
A configurable computing array is introduced, comprising arrays of configurable interconnects, logic elements, and computing elements with programmable memories that can store look-up tables for math functions, allowing for reconfiguration and efficient hardware computation of complex math functions by decomposing them into basic functions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional processors use logic-based computation with fixed logic circuits for math functions, then hardware implementation is achieved, but the hardware resources are limited and highly customized for each function, reducing adaptability
Solution Approach 1:
The patent implements a universal math function unit that can execute multiple math functions (exponential, logarithmic, trigonometric, etc.) through a single hardware structure. The unit uses configurable parameters and a unified computation framework to perform different functions, eliminating the need for separate customized hardware circuits for each math function while maintaining hardware execution reliability
2Adaptability or versatility
If conventional processors implement math functions using software computing, then adaptability to various functions is improved, but computational speed and efficiency deteriorate
Solution Approach 1:
The patent replaces software-based math function computation with a dedicated hardware math function unit. This unit uses electrical/circuit-based computation to execute math functions directly in hardware, providing both the versatility of software (through configurable parameters) and the speed of hardware execution, thus substituting the slower software mechanical process with faster hardware operation
3Measurement precision
If conventional processors use fixed logic circuits for each math function, then computation precision is maintained, but device complexity and resource requirements increase
Solution Approach 1:
The patent merges multiple separate math function circuits into a single unified math function unit. This consolidated unit uses shared computational resources, configurable parameters, and a common execution framework to maintain precision across all math functions while significantly reducing overall hardware complexity and resource requirements compared to having separate fixed circuits for each function
Data Source
AI summary
A configurable computing array comprises at least an array of configurable interconnects, at least an array of configurable logic elements and at least an array of configurable computing elements. Each configurable computing element comprises at least a programmable memory for storing a look-up table (LUT) for a math function.