Configurable Delay Circuits for Multi-Memory Data Timing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In multi-memory systems, timing differences between memory units can cause data collisions at the shared data pipeline, leading to operational inefficiencies due to the lack of accounting for relative timing characteristics between individual memory units.
Innovation Solution
The implementation of configurable delay circuits in both the master and slave memory units to delay data provision to the data pipeline, matching the timing characteristics of the slowest memory unit, thereby preventing data collisions by synchronizing data access operations across memory units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If delta timing between consecutive memory access commands is used to control data flow, then data flow control is simplified, but data collisions occur at the data pipeline due to timing differences between memory units
Solution Approach 1:
A timing adjustment circuit is introduced as an intermediary component between the memory units and the shared data pipeline. This circuit receives data from multiple memory units and adjusts their timing characteristics before data is provided to the data pipeline, preventing data collisions without complicating the overall data flow control mechanism
Solution Approach 2:
The timing characteristics of data output from individual memory units are modified by changing the timing parameters through the timing adjustment circuit. This allows synchronization of data output timing across multiple memory units with different inherent timing characteristics, ensuring reliable operation of the shared data pipeline
2Speed
If minimum timing requirements between consecutive access commands are compressed, then access speed is improved, but timing differences between memory units cause data collisions
Solution Approach 1:
The timing adjustment circuit serves as a mediator that allows compressed timing between access commands while compensating for timing differences between memory units. It receives rapidly successive commands and adjusts the timing of data output from each memory unit to prevent collisions, enabling high-speed operation without sacrificing reliability
3Adaptability or versatility
If individual memory units operate with their own timing characteristics, then each unit operates independently, but data collisions occur at the shared data pipeline
Solution Approach 1:
The timing adjustment circuit acts as an intermediary that preserves the independence of individual memory units while coordinating their data output timing. Each memory unit continues to operate with its own timing characteristics, but the timing adjustment circuit synchronizes their data provision to the shared pipeline, preventing collisions
Solution Approach 2:
The timing adjustment circuit creates equipotential timing conditions at the data pipeline interface by compensating for timing differences between memory units. This ensures that data from different memory units arrives at the pipeline in a synchronized manner, eliminating timing-related conflicts while maintaining unit independence
Data Source
AI summary
Apparatuses, mufti-memory systems, and methods for controlling data timing in a multi-memory system are disclosed. An example apparatus includes a plurality of memory units. In the example apparatus, a memory unit of the plurality of memory units includes a memory configured to provide associated read data to a data pipeline based on row control signals and column control signals. The memory unit further includes local control logic configured to provide the row control signals and the column control signals to the memory, and a configurable delay circuit coupled between the local control logic and the memory, the configured to delay receipt of the column control signals to the memory.