Digital Storage TRIZ Cases

A phase-change memory device uses stacked contact holes to reduce current requirements for data writing.

A semiconductor apparatus uses a multiplexing circuit to selectively output latched signals as feedback commands through DQ pins.

A resistive memory device separates write and read currents into distinct signal lines to minimize thermoelectric effects.

Segmented capacitors isolate the write driver ground path, preventing boost charge leakage and maintaining bit line strength.

Assembling 2R1W memories into banks reduces area overhead and power consumption while enabling port extension in Ethernet switch chips.

Replacing software decoding with a memristor array reduces hardware volume and power consumption while maintaining signal processing capability.

Applying alternating polarity voltages strengthens conductive filaments, narrowing resistance distributions and improving RRAM retention.

Configurable delay circuits adjust column control signal timing to prevent data collisions at the shared pipeline.

Segmented GIO termination units activate selectively via control signals, reducing coupling noise and power waste during high-speed memory operations.

A unified driver architecture connects access lines across multiple decks to balance RC load, reducing wiring complexity in multideck memory arrays.

A memory device adjusts write current intensity using a current controller and replica memory cells to optimize operation conditions.

Alternative shaped macro blocks use notches to place reserved areas, eliminating wide channels and increasing die area efficiency.

A semiconductor test circuit inverts input data bits to generate internal data with varied topologies.

A memory controller adjusts power supply voltage and clock frequency to generate register codes that select fast or slow mode input output circuits.

A semiconductor storage device applies a dummy voltage to dummy word lines in phase with selected word voltages.

Buffer control signal generation circuit synchronizes with write commands to stabilize input signals, preventing malfunctions from unstable data strobes.

Merging field generation and heating into one current line lowers power consumption and increases cell density by reducing required CMOS metal levels.

Heterogeneous tunnel junction structure combines electric field control with spin transfer torque for low power memory operation.

Eliminating notch structures removes manufacturing precision constraints while spin orbital torque stabilizes domain wall movement for reliable data storage.

A signal holding circuit generates reference voltages from sample data to enable high-accuracy detection in magnetic random access memory.

Additional power voltage maintaining unit prevents internal clock timing instability and voltage drops in DLL circuits during power down recovery.

A semiconductor memory output buffer uses a replica circuit to adjust transistor states for consistent impedance matching.

Segmented power rails and dynamic voltage control resolve the trade-off between read stability and write speed in advanced SRAM nodes.

Applying an additional magnetic field assists electron current to switch the magnetic free layer, reducing power consumption and preventing electron migration.

Thick-film transistors in the precharge circuit withstand high activation voltages, resolving speed-reliability trade-offs without separate power supplies.

A line defect detection circuit integrated into semiconductor memory devices identifies column selection line faults during test operations.

A variable reference resistor adjusts its resistance via calibration codes to maintain data reading accuracy in resistive memory cells.

A standby leakage current reduction circuit adjusts virtual ground voltage via a bias signal generator to minimize power drain.

Logic circuitry multiplexes data bursts across ranks on a shared strobe signal to double per-pin bandwidth.

Refresh circuitry performs opportunistic memory bank updates using a scoreboard to track pending transactions and refresh status.

Temperature sensing generates voltages compared to adjust the self refresh cycle, eliminating manual EMRS code settings for stable operation.

A tri-level DRAM sense amplifier uses isolated sub-amplifiers to detect binary and neutral data states on complementary digit lines.

A memory access interface device generates valid strobe pulses to sample data signals accurately.

A memory storage apparatus switches operating modes to adjust refresh frequencies and voltages for efficient data retention.

A memory testing circuit routes comparison data to an internal comparator and captures match signals for standard self-test reporting.

A multi-stage linear receiver architecture with programmable voltage swings and delays adjusts signal timing.

In-cell differential read-out circuitry generates signed weight currents directly from resistive processing unit cells.

Integrating a ferroelectric layer with an amorphous chalcogenide switching layer expands the read memory window and improves data storage reliability.

Maskable memory cells use block-level mask signals to suppress unnecessary data during access.

A semiconductor memory device uses thermal energy storage to change electrical properties without additional refresh voltages.

Segmented memory cells route operations by access duration, reducing stress cycling effects that accelerate leakage current and bit errors.

A dynamic shift register circuit design minimizes voltage at the cross point of adjacent output pulses.

Enzymatic synthesis assembles DNA strands to store digital data, addressing limited lifespan and high maintenance costs of traditional media.

An unselected bitline provides a reference voltage for differential sensing, eliminating separate generators to reduce power consumption.

A calibration control circuit compares power voltage with reference voltages to determine the logic state of a calibration command signal.

Data hubs group clients by physical position to process burst data and store it in target memory via a control protocol.

A magnetic tunnel junction latch retains state information magnetically without continuous power.

A semiconductor memory apparatus uses an operation mode signal generation unit to create mode signals from bonding and control inputs.