Dynamic Shift Register Circuit Minimizing Pulse Overlap
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Solution Overview
Problem
In dynamic shift register circuits for TFT-LCDs, overlapping between adjacent clock signals leads to incorrect data reception by pixel arrays, resulting in distorted display images and unstable display quality.
Innovation Solution
A dynamic shift register circuit design comprising multiple shift register units connected in series, each with specific transistor assemblies and configurations to minimize the voltage at the cross point of adjacent output pulses, using clock and inverse clock signals to control the flow of signals and reduce overlap.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a prior dynamic shift register circuit is used, then the circuit can output clock signals for driving scanning lines and signal lines, but overlapping occurs between adjacent output pulses causing incorrect data reception and display distortion
Solution Approach 1:
The patent introduces a control signal as an intermediary element that mediates between adjacent shift register units. This control signal dynamically adjusts the timing or characteristics of output pulses to prevent overlapping, thereby resolving the harmful effect while maintaining reliable data transmission to pixel arrays
Solution Approach 2:
The invention implements dynamic control of the shift register circuit operation. By making the circuit characteristics adjustable through control signals rather than fixed, the system can adaptively prevent signal overlapping conditions, improving reliability without requiring a completely different circuit architecture
2Reliability
If the overlapping between adjacent clock signals is reduced, then data reception accuracy improves, but the circuit complexity increases due to additional control mechanisms
Solution Approach 1:
The patent designs the shift register units to perform multiple functions: they not only generate clock signals for driving scanning lines and signal lines but also inherently control the timing of adjacent outputs through integrated control logic. This multi-functionality reduces the need for separate overlapping prevention circuits, thereby limiting the increase in device complexity while improving display stability
Data Source
AI summary
An improved dynamic shift register circuit is disclosed. A circuit design is provided to minimize overlapping between two adjacent output pulses in the dynamic shift register circuit. In an application of analog sample-and-hold circuit, the circuit design effectively improves a distortion of sampled data caused by significant overlapping of two adjacent output pulses as control signals.