Semiconductor Test Circuit Using Data Inversion for Parallel Testing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices become more integrated, the test time required to evaluate their characteristics increases, necessitating the inclusion of self-test circuits to reduce test time and production cost, particularly in compressive parallel tests where data is stored in memory cells to detect errors.
Innovation Solution
A semiconductor device with a control signal generator and data input units that invert input data bits based on decoded signals and test enable signals to generate internal data with different topologies, allowing for efficient testing without additional data pads, reducing test time and area occupancy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor devices become more highly integrated, then device functionality and capacity are improved, but test time increases
Solution Approach 1:
The patent divides the test process into multiple test modes (first test mode and second test mode) that can be executed alternately. The test memory is segmented into different cell arrays (first cell array, second cell array, third cell array) that can be tested independently in different modes, allowing parallel testing operations and reducing overall test time for highly integrated devices.
Solution Approach 2:
The patent implements periodic alternation between different test modes. The test controller alternates between the first test mode (using first and second cell arrays) and the second test mode (using third cell array), creating a periodic testing rhythm that maximizes the utilization of available test resources and reduces total test time compared to sequential testing of all cell arrays.
2Loss of time
If self test circuits are embedded to reduce test time, then test time is reduced, but device complexity increases
Solution Approach 1:
The patent designs a multi-functional test circuit that can operate in different test modes using the same basic circuitry. The test controller, data input units, and cell arrays serve multiple purposes: they can function in first test mode with specific configurations and in second test mode with different configurations, eliminating the need for separate dedicated circuits for each test type and reducing overall device complexity.
Solution Approach 2:
The patent implements dynamic reconfiguration of the test circuit through control signals that can switch between different test modes. The data input units can dynamically invert or pass through data bits based on control signals, and the test controller can dynamically select which cell arrays to test and in what mode, allowing the circuit to adapt its behavior without requiring multiple static circuit configurations.
3Reliability
If different kinds of tests are performed by storing data with different topologies, then test coverage is improved, but data input complexity increases
Solution Approach 1:
The patent uses data inversion as a systematic approach to generate different data topologies. Instead of requiring completely different data patterns for different test modes, the system stores data in a standard format and then inverts specific bits (first bit, second bit, third bit) using control signals during the test process. This inversion mechanism efficiently creates varied data topologies for comprehensive test coverage while keeping the data input process simple and uniform.
Data Source
AI summary
Semiconductor devices are provided. The semiconductor device includes a control signal generator and a first data input unit. The control signal generator generates an inverted control signal including a first bit and a second bit using a decoded signal in response to a test enable signal. The first data input unit inverts a first bit of input data in response to the first bit of the inverted control signal to generate a first bit of first internal data. Further, the first data input unit inverts a second bit of the input data in response to the second bit of the inverted control signal to generate a second bit of the first internal data.