Memory Testing Circuit for Internal Comparator Self-Test
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Solution Overview
Problem
Commercial built-in self-test (BIST) designs for memory devices are unable to test specialized functionalities, such as internal comparators, leading to potential operational failures that go undetected.
Innovation Solution
A memory testing circuit is introduced to test features like internal comparators by modifying output values to indicate comparison failures, allowing self-test circuits to report errors even if they cannot directly test these components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a standardized self-test circuit is used, then the testing device can be reused across different memory devices, but it cannot test specialized functionality such as internal comparators
Solution Approach 1:
A memory testing circuit is introduced as an intermediary component between the standardized self-test circuit and the memory device. This intermediary circuit receives test signals from the self-test circuit, performs specialized comparison operations using the internal comparator, and translates the results into formats the self-test circuit can interpret. This allows the standardized self-test circuit to indirectly test specialized functionality like internal comparators that it cannot directly access.
Solution Approach 2:
The testing system is divided into separate functional modules: the standardized self-test circuit, the memory testing circuit, and the memory device. This segmentation allows each component to have specialized functionality - the self-test circuit remains universal while the memory testing circuit handles specialized comparison operations, and the memory device provides the test subject. This modular approach resolves the contradiction by allowing specialized testing capability without sacrificing the universality of the self-test circuit.
2Ease of manufacture
If commercial BIST designs are used, then a set of standard functions can be verified, but additional hardware functionality such as internal comparators cannot be tested
Solution Approach 1:
The memory testing circuit is designed with multi-functionality to handle both standard memory operations and specialized comparison operations. It can receive test signals for standard functions and simultaneously execute comparison operations using the internal comparator. This universal design allows a single circuit to verify both standard functions and additional hardware functionality, resolving the limitation of commercial BIST designs while maintaining ease of manufacture through standardized approaches.
3Device complexity
If the self-test circuit cannot directly test the internal comparator, then the testing system remains simple, but comparison failures go undetected
Solution Approach 1:
The memory testing circuit utilizes the memory device's own internal resources (including the internal comparator) to perform the testing function. Instead of requiring external complex test equipment, the system leverages the memory's built-in comparator to compare test values and generate match/mismatch signals. This self-service approach maintains relative simplicity while enabling detection of comparison failures, as the memory device tests itself using its inherent hardware capabilities.
Data Source
AI summary
In some embodiments, a system includes a memory testing circuit configured to perform a test of an internal comparator of a memory circuit by performing operations. The operations may include causing a first value to be stored at the memory circuit as a current data value. The operations may further include subsequently causing the first value to be sent to the memory circuit as a current comparison data value. The operations may further include causing the internal comparator to compare the current data value to the current comparison data value. The operations may further include receiving a current match value that indicates whether the current data value matches the current comparison data value. In some embodiments, the memory testing circuit may be configured to enable a self-test circuit to detect errors regarding functions of the memory circuit that the self-test circuit is not designed to test.