Dynamic I/O Buffer Control for Low Pin Count Memory Power Optimization
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Solution Overview
Problem
Low pin count memory devices in IoT and wearable devices face high current consumption due to high clock frequencies, leading to short battery life, as conventional technologies do not dynamically adjust access time based on clock frequency and operation mode.
Innovation Solution
A memory device with a pseudo static random access memory and a controller that adjusts power supply voltage and clock frequency to generate a register setting code, enabling either a fast mode or slow mode circuit in the input/output circuit, dynamically adjusting access time and providing power-saving control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high clock frequency is used in low pin count memory, then data transmission speed is improved, but current consumption increases
Solution Approach 1:
The patent applies dynamics by making the input/output circuit configuration changeable between fast mode and slow mode based on operation requirements. The controller dynamically selects between different circuit modes (fast mode circuit with first input buffer and second output buffer, or slow mode circuit with third input buffer and fourth output buffer) to match the required data transmission speed, thereby avoiding unnecessary high current consumption when high speed is not needed.
Solution Approach 2:
The patent changes the parameter of circuit operation mode between fast mode and slow mode. By adjusting the operational parameters (buffer configuration, circuit path selection) based on the required data transmission speed, the system can operate at different performance levels, consuming less current when lower speed suffices while maintaining high speed capability when required.
2Adaptability or versatility
If independent control of current driving force is used, then operational flexibility is improved, but battery life decreases
Solution Approach 1:
The patent implements dynamic control by linking the current driving force adjustment to the operation mode. The controller configures the input/output circuit differently based on whether fast mode or slow mode is required, and simultaneously adjusts the current driving force to match. This prevents unnecessary high current consumption when slow mode operation suffices, thereby extending battery life while maintaining operational flexibility.
Solution Approach 2:
The system uses feedback by having the controller determine the appropriate operation mode based on system requirements and then configure both the circuit mode and current driving force accordingly. This closed-loop approach ensures that current consumption is optimized for each operational state, improving battery life while preserving the ability to adapt to different operational requirements.
Data Source
AI summary
A memory device and a method for input/output buffer control are provided. The memory device includes a pseudo static random access memory and a controller. The pseudo static random access memory includes an input/output circuit having a fast mode circuit and a slow mode circuit. The controller adjusts a power supply voltage and a clock frequency according to an operation mode of the memory device, and generates a register setting code based on an adjusted power supply voltage and an adjusted clock frequency. The pseudo static random access memory enables one of the fast mode circuit and the slow mode circuit according to the register setting code, and disables the other of the fast mode circuit and the slow mode circuit.