Single-Ended Bitline Memory Reference Voltage Generation
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Solution Overview
Problem
Memory devices with single-ended bitline structures require additional reference voltage generators, leading to increased power consumption and chip area due to the need for circuits like band gap references and voltage generation circuits during read operations.
Innovation Solution
A memory device with a reference voltage generator that outputs the bitline voltage of a selected memory cell array as a sensing voltage and the bitline voltage of an unselected array as a reference voltage, using complementary logic states, thereby reducing the need for separate voltage generation circuits and minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a separate reference voltage generator is used in single-ended bitline memory devices, then accurate data sensing is achieved, but power consumption increases
Solution Approach 1:
The patent merges the reference voltage generation function with the existing bitline structure by repurposing the unselected bitline as the reference voltage source. Instead of using a separate reference voltage generator, the system combines the sensing function (using selected bitline) and reference function (using unselected bitline) into a unified architecture, thereby eliminating additional power-consuming circuits while maintaining sensing accuracy
Solution Approach 2:
The unselected bitline, which would traditionally remain idle or require dedicated reference generation circuits, is赋予 dual functionality: it serves both as a physical structure already present in the memory array and as the reference voltage source for the differential sense amplifier. This multi-functional use eliminates the need for separate reference voltage generation circuits, reducing power consumption while maintaining accurate data sensing capability
2Measurement precision
If a separate reference voltage generator is used in single-ended bitline memory devices, then accurate data sensing is achieved, but chip area increases
Solution Approach 1:
The patent merges the reference voltage generation function with the existing bitline structure by repurposing the unselected bitline as the reference voltage source. Instead of using a separate reference voltage generator, the system combines the sensing function (using selected bitline) and reference function (using unselected bitline) into a unified architecture, thereby eliminating additional power-consuming circuits while maintaining sensing accuracy
Solution Approach 2:
The unselected bitline, which would traditionally remain idle or require dedicated reference generation circuits, is赋予 dual functionality: it serves both as a physical structure already present in the memory array and as the reference voltage source for the differential sense amplifier. This multi-functional use eliminates the need for separate reference voltage generation circuits, reducing power consumption while maintaining accurate data sensing capability
3Reliability
If multiple voltage generation circuits are implemented, then reference voltage is provided, but device complexity increases
Solution Approach 1:
The patent extracts the reference voltage generation function from the category of active voltage generation circuits and reassigns it to the passive unselected bitline structure. By taking out the need for separate band gap reference circuits and voltage generation circuits, the system maintains reliable reference voltage provision through the natural voltage difference between selected and unselected bitlines, thereby reducing device complexity
Solution Approach 2:
The unselected bitline automatically serves as the reference voltage source without requiring external control or additional generation circuits. The system utilizes the inherent voltage state of the unselected bitline (which remains at precharge or discharge level) to provide the reference voltage, eliminating the need for complex voltage generation control logic and reducing overall device complexity
Data Source
AI summary
A memory device includes a first memory cell array including memory cells of a single-ended bitline structure, a second memory cell array including memory cells of a single-ended bitline structure, a reference voltage generator configured to output a bitline voltage of a selected one of the first and second memory cell arrays as a sensing voltage according to an array select signal and output a bitline voltage of an unselected memory cell array as a reference voltage, and a differential sense amplifier configured to amplify and output a difference between the sensing voltage and the reference voltage. Logic states of the sensing voltage and the reference voltage are complementary to each other.


