Memory Access Interface Device Skew Compensation Sampling
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Solution Overview
Problem
Conventional memory data reading technologies struggle to accurately sample data signals at high speeds due to the skew between data signals and data strobe signals, which is exacerbated by the high clock frequencies in modern memory devices like DDR5 and LPDDR5, leading to inaccurate data reading.
Innovation Solution
A memory access interface device comprising a data processing circuit, a sampling clock generation circuit, and a control circuit that processes data signals and generates valid strobe pulses and sampling clock signals, allowing for accurate sampling by adjusting the timing and eliminating tri-state sections to ensure valid data extraction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high clock frequency is used to increase memory speed, then memory transmission speed is improved, but the skew between data signal and data strobe signal increases causing inaccurate sampling
Solution Approach 1:
The patent applies dynamics by making the sampling clock generation adaptable to varying skew conditions. The sampling clock generation circuit dynamically adjusts the phase and timing of sampling clocks based on the actual skew between data signal and data strobe signal, allowing the system to maintain accurate sampling despite high-speed transmission. This is achieved through detect circuits that measure skew and control circuits that adjust sampling timing accordingly.
Solution Approach 2:
The patent changes the timing parameters of the sampling clock signal to compensate for skew. By adjusting the phase shift amount and timing offset of sampling clocks based on detected skew conditions, the system maintains accurate data sampling. The control circuit modifies sampling clock parameters (phase, timing) in response to measured skew, effectively counteracting the adverse effects of high-speed transmission.
2Measurement precision
If data strobe signal timing is adjusted to reduce skew, then sampling accuracy is improved, but the flexibility to handle both high-speed and low-speed memory devices is reduced
Solution Approach 1:
The patent achieves universality by designing a sampling system that can adapt to different memory device types and speeds. The detect circuit measures skew for any memory device, and the control circuit adjusts sampling clock timing accordingly. This multi-functional approach allows the same hardware to accurately sample data from both high-speed devices (with large skew) and low-speed devices (with small skew) by dynamically adjusting to each device's characteristics.
Solution Approach 2:
The system dynamically adapts its sampling timing to match the specific characteristics of connected memory devices. Rather than using fixed timing adjustments, the system continuously detects skew and adjusts sampling clock parameters in real-time, enabling compatibility across different device types and speeds while maintaining sampling accuracy.
3Device complexity
If conventional sampling method is used, then device complexity is low, but false sampling occurs due to time difference between strobe and data signals
Solution Approach 1:
The patent introduces intermediary circuits (detect circuits and control circuits) that measure skew and adjust sampling timing. These intermediary components act as mediators between the data strobe signal and the sampling clock generation, allowing the system to compensate for skew and eliminate false sampling. The detect circuit measures the time difference, and the control circuit uses this information to adjust sampling clock timing, preventing false data capture.
Solution Approach 2:
The system implements feedback by using detect circuits to measure skew and feed this information back to control circuits that adjust sampling clock timing. This closed-loop feedback mechanism continuously monitors sampling conditions and makes real-time adjustments to maintain accurate data capture, significantly improving reliability compared to open-loop conventional sampling methods.
Data Source
AI summary
The present disclosure discloses a memory access interface device. A data processing circuit receives a data signal including 2M pieces of data from a memory device. A sampling clock generation circuit receives a data strobe signal from the memory device to generate a valid data strobe signal having P valid strobe pulses and further generate a sampling clock signal accordingly, in which P is larger than M. A sampling circuit samples the data signal according to the sampling clock signal to generate sampling results. A control circuit determines valid sampling results according to a time difference between the valid data strobe signal and the data signal and outputs valid data generated according to the valid sampling results as a read data signal to a memory access controller.