SDRAM DIMM Multiplexing Logic for Increased Data Pin Bandwidth
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Solution Overview
Problem
Current memory channel designs, such as those in DDR5, still employ a multi-drop bus approach that limits memory channel bandwidth and operating frequency, despite attempts to increase memory capacity and reduce signal loading.
Innovation Solution
The implementation of a point-to-point (P2P) data bus architecture, where each DIMM is connected directly to the host via separate P2P data busses, allowing for multiplexing of data transfers between ranks over a burst time window, effectively doubling the bandwidth by transferring 32-bit data between two ranks on each bus.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a multi-drop bus approach is used to connect DIMMs to the memory controller, then memory channel capacity can be increased, but memory channel bandwidth and operating frequency are limited due to signal loading
Solution Approach 1:
The patent segments the memory channel interface into multiple independent point-to-point data busses (DQ0 and DQ1) instead of using a shared multi-drop bus. Each DIMM is connected to the memory controller via its own dedicated data bus, eliminating signal loading issues and enabling higher bandwidth while maintaining the ability to support multiple DIMMs through the segmented bus architecture.
Solution Approach 2:
The patent introduces an intermediary multiplexer that allows a single memory channel to interface with multiple DIMMs through separate point-to-point data busses. The multiplexer mediates between the memory controller and multiple DIMMs, enabling bandwidth doubling by transferring 32-bit data between two ranks on each bus while maintaining efficient operation through multiplexing.
2Quantity of substance
If memory channel capacity is increased to improve system memory performance, then power consumption of the memory channel implementation increases
Solution Approach 1:
The patent implements dynamic multiplexing on the data busses where data transfers between different ranks are multiplexed over the same physical bus infrastructure. This dynamic sharing of bus resources allows the system to achieve doubled bandwidth capacity without proportionally increasing power consumption, as the same physical channels are reused through time-division multiplexing.
Data Source
AI summary
An apparatus is described. The apparatus includes logic circuitry to multiplex on a data bus a first data burst, a second data burst, a third data burst and a fourth data burst having different respective base target addresses that respectively target a first memory rank, a second memory rank, a third memory rank and a fourth memory rank. A first data transfer for the first data burst occurs on a first edge of a first pulse of a data strobe signal for the data bus and a second data transfer for the second data burst occurs on a second edge of the first pulse of the data strobe signal. A third data transfer for the third data burst occurs on a first edge of a second pulse of the data strobe signal for the data bus and a fourth data transfer for the fourth data burst occurs on a second edge of the second pulse. The second pulse immediately follows the first pulse on the data strobe signal. The first memory rank, the second memory rank, the third memory rank and the fourth memory rank are on a same memory module.