Resistive Memory Device Signal Line Segmentation for Read Disturb
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Solution Overview
Problem
Resistive memory devices face degradation due to spike currents occurring during data reading operations, which can lead to data reliability issues.
Innovation Solution
The design includes a resistive memory device with separate signal lines for write and read currents, where the write current flows from a first signal line to a second signal line through the memory cell during writing, and the read current flows in the opposite direction during reading, utilizing different signal paths to minimize thermoelectric effects and reduce spike current-induced disturbances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If read current is supplied through the same signal line as write current, then device complexity is reduced, but spike current-induced read disturb occurs causing data reliability degradation
Solution Approach 1:
The patent segments the signal lines into two distinct sets: first signal lines (word lines) for supplying write current and second signal lines (bit lines) for supplying read current. This segmentation separates the write and read operations into different physical paths, preventing spike current from affecting non-selected memory cells during read operations, thereby resolving the contradiction between device simplicity and data reliability.
2Device complexity
If write current and read current flow in the same direction, then circuit design is simplified, but thermoelectric effects cause heat transfer and resistance distribution changes
Solution Approach 1:
The patent inverts the conventional current flow direction by having write current flow from first signal line to second signal line through the memory cell, while read current flows from second signal line to first signal line. This reverse direction arrangement for read current counteracts thermoelectric heat transfer effects, preventing temperature-induced resistance changes and eliminating the contradiction between simplified circuit design and thermal stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces spike current-induced read disturb (SIRD) and enhances data reliability by controlling the direction of currents during write and read operations, thereby minimizing heat transfer and maintaining resistance distributions.
Implementation Method 1
a write circuit configured to supply a write current to at least one memory cell of the plurality of memory cells through at least one first signal line of the plurality of first signal lines, the write current associated with writing data in the at least one memory cell
Implementation Method 2
a read circuit configured to supply a read current to the at least one memory cell of the plurality of memory cells through at least one second signal line of the plurality of second signal lines, the read current associated with reading data stored in the at least one memory cell
Implementation Method 3
resistive memory devices to which write currents and read currents are applied in different directions... minimize heat transfer and maintaining resistance distributions
Data Source
AI summary
A resistive memory device includes a memory cell array including a memory cell connected between a first signal line and a second signal line, an instance of control circuitry configured to generate a write control signal to control a data writing operation performed on the memory cell and a read control signal to control a data reading operation of reading data stored in the memory cell, a write circuit configured to supply a write current to support the data writing operation, a read circuit configured to supply a read current to support the data reading operation, a column decoder circuit configured to electrically connect the write circuit to the first signal line, based on the write control signal; and a row decoder circuit configured to electrically connect the read circuit to the second signal line, based on the read control signal.