Memory Storage Apparatus Multiple Refresh Modes Voltage Optimization
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Solution Overview
Problem
Dynamic random access memory (DRAM) devices face power consumption issues due to electric leakage in capacitors, leading to data loss, and require frequent refresh modes to maintain data integrity, which is problematic for low-power portable devices.
Innovation Solution
A memory storage apparatus with multiple operating modes, including a second mode with reduced operating voltage, allows for efficient data refresh with lower power consumption, and a fourth mode that temporarily suspends data refresh to conserve power, along with specific voltage and reference voltage management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory storage apparatus operates in refresh mode to maintain data integrity, then data correctness is ensured, but power consumption increases
Solution Approach 1:
The patent implements multiple operating modes (first, second, third, and fourth modes) that dynamically adjust the refresh operation characteristics. The memory storage apparatus can switch between different refresh strategies based on system requirements, enabling adaptive power management while maintaining data integrity when needed.
Solution Approach 2:
The patent changes operating parameters by implementing different refresh modes with varying refresh frequencies and voltage levels. The first operating mode uses a first refresh frequency, while the second operating mode uses a second refresh frequency that is lower than the first, directly reducing power consumption during refresh operations.
2Reliability
If the refresh frequency is increased to maintain data integrity, then data correctness is improved, but power consumption increases
Solution Approach 1:
The system dynamically adjusts refresh frequency based on the operating mode. In the first operating mode, a higher first refresh frequency maintains data integrity, while in the second operating mode, a lower second refresh frequency reduces power consumption, allowing the system to adapt to different performance and power requirements.
Solution Approach 2:
The patent directly changes the refresh frequency parameter between operating modes. By implementing a second refresh frequency that is lower than the first refresh frequency in the second operating mode, the system optimizes the balance between data correctness and power consumption for low-power applications.
3Use of energy by moving object
If the operating voltage is reduced to save power, then power consumption decreases, but data refresh effectiveness may be compromised
Solution Approach 1:
The patent changes the operating voltage parameter by implementing a second operating voltage that is lower than the first operating voltage in the second operating mode. This voltage reduction directly decreases power consumption while the system maintains data refresh effectiveness through the optimized second refresh frequency and multiple mode architecture.
Data Source
AI summary
A memory storage apparatus having a plurality of operating modes is provided. The memory storage apparatus includes a memory control circuit and a memory cell array circuit. The memory control circuit controls the memory storage apparatus to operate in one of the operating modes. The memory control circuit controls the memory storage apparatus to operate in a first operating mode and controls the memory storage apparatus to switch from the first operating mode to a second operating mode to refresh storage data of the memory cell array circuit. The memory storage apparatus operates in a third operating mode to refresh storage data in the memory storage apparatus. An operating voltage of the memory storage apparatus operating in the second operating mode is smaller than an operating voltage of the memory storage apparatus operating in the third operating mode.