Irregular Memory Macro Blocks with Sidecar Arrays
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing methods for floor planning semiconductor chips face inefficiencies due to the constraints imposed by the dimensions of memory macro blocks, which often require significant redesign and result in unused space due to the need for wide channels to accommodate reserved areas for through silicon vias (TSVs) and other components, making it difficult to fit all components within the same die or package.
Innovation Solution
The use of alternative shaped memory macro blocks such as cross-shaped, T-shaped, or L-shaped blocks that utilize primary and sidecar arrays to store memory lines, allowing reserved areas to be placed in the notches of these blocks, eliminating the need for wide channels and increasing area efficiency by filling previous empty spaces with additional memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If rectangular memory macro blocks are used with traditional floor planning, then memory capacity is achieved, but significant unused space is created due to wide channels required for reserved areas
Solution Approach 1:
The memory array is segmented into multiple banks arranged in a grid pattern, with reserved areas strategically positioned at intersections. This segmentation allows efficient space utilization by filling previously wasted channel areas with additional memory banks, transforming unused space into functional memory capacity.
Solution Approach 2:
Multiple memory banks are merged into a unified memory structure with shared control logic and integrated reserved areas. The reserved areas serve dual purposes: providing necessary routing space and acting as additional memory capacity through the bank structure, thereby eliminating wasted space while maintaining functionality.
2Ease of manufacture
If memory macro block dimensions are increased to accommodate reserved areas, then routing requirements are met, but the die size increases and other components cannot fit
Solution Approach 1:
The memory structure transitions from traditional rectangular blocks to a three-dimensional bank grid arrangement. Reserved areas are positioned at vertical intersections in this multi-dimensional layout, allowing routing space to be integrated without increasing the horizontal die footprint, thus enabling other components to fit within the same package.
3Device complexity
If traditional rectangular memory blocks are used, then simple structure is maintained, but significant redesign is required to fit other components
Solution Approach 1:
The memory bank structure serves multiple functions simultaneously: it provides organized memory capacity, integrates reserved areas for routing at intersections, and enables flexible floor planning. The grid arrangement of banks can be adapted to various die layouts and component placements, making the design versatile without increasing complexity.
Data Source
AI summary
A system and method for floorplanning a memory. A computing system includes a processing unit which generates memory access requests and a memory. The size of each memory line in the memory includes M bits. A memory macro block includes at least a primary array and a sidecar array. The primary array stores a first portion of a memory line and the sidecar array stores a second smaller portion of the memory line being accessed. The primary array and the sidecar array have different heights. The height of the sidecar array is based on a notch height in at least one corner of the memory macro block. The notch creates on-die space for s reserved area on the die. The notches result in cross-shaped, T-shaped, and/or L-shaped memory macro blocks.