Semiconductor Command Training Circuit Using Flag Signal Feedback

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Solution Overview

Problem

Conventional semiconductor apparatuses require lengthy command training processes due to the need for repeated MRS setting and command transmission/reception in multiple modes, increasing training time significantly.

Innovation Solution

A semiconductor apparatus and command training system that includes a command receiving circuit, a multiplexing circuit, and a DQ circuit, which latch signal bits based on a clock signal and use an internally generated flag signal to selectively output feedback commands through DQ pins, reducing the need for repeated MRS setting and command transmission.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the conventional semiconductor apparatus performs command training through multiple modes (rising edge mode, falling edge mode, rising & falling edge mode) with repeated MRS setting and command transmission/reception, then the command training can be completed comprehensively, but the command training time is significantly increased

Engineering Contradiction:
Improvecommand training completenessVSAvoidcommand training time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The feedback command signal is segmented into multiple components: latched command signals (CA0-CA9) and a flag signal. The flag signal is segmented to indicate different feedback modes (rising edge, falling edge, or both), allowing the system to convey mode information without requiring separate MRS settings for each mode.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent merges the command feedback function with mode indication by combining the latched command signals with a flag signal in the same feedback path. This consolidation eliminates the need for separate MRS setting operations for different feedback modes, reducing training time while maintaining comprehensive command training across all modes.

Inventive Principle:
Principle #5Merging (Combining)

2Adaptability or versatility

If the semiconductor apparatus uses the DQ circuit to feed back received commands to the controller, then command training can be performed, but when the number of feedback signals exceeds the number of DQ pins, the apparatus must sequentially transmit feedback signals using MRS setting, increasing training time

Engineering Contradiction:
Improvefeedback signal transmission capabilityVSAvoidcommand training time
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The flag signal serves multiple functions: it indicates the feedback mode (rising edge, falling edge, or both), and it enables the DQ circuit to efficiently multiplex multiple command feedback signals through the limited DQ pins. This multi-functionality allows comprehensive command training without requiring sequential transmission procedures.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The flag signal acts as an intermediary that carries mode information and control instructions between the command receiving circuit and the DQ circuit. This intermediary enables the system to switch between different feedback modes dynamically without requiring separate MRS setting operations, thereby reducing training time while maintaining adaptability.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11210250B2Semiconductor apparatus, command training system, and command training method
Publication Date: 2021.12.28 SK HYNIX INC
  • US11210250B2 patent drawing
  • US11210250B2 patent drawing
  • US11210250B2 patent drawing

AI summary

A semiconductor apparatus may include a command receiving circuit, a multiplexing circuit, and a DQ circuit. The command receiving circuit may be configured to latch signal bits of a command according to a clock signal, and output the latched signal bits as latched signals. The multiplexing circuit may be configured to receive the latched signals from the command receiving circuit, and selectively output the latched signals according to a flag signal which is internally generated within the semiconductor apparatus. The DQ circuit may be configured to receive the selectively outputted latched signals from the multiplexing circuit and receive the flag signal, and configured to output the selectively outputted latched signals and the flag signal as a feedback command to the outside of the semiconductor apparatus through a plurality of DQ pins.