Scalable Multi-Port Memory via 2R1W Bank Assembly
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Solution Overview
Problem
Existing multi-port memory designs for Ethernet switch chips face challenges in achieving high core frequencies and scalability due to large area overhead and high power consumption, particularly when expanding from 4 slices to 8 or more, and require complex control logics and additional resources.
Innovation Solution
A data processing method and system that constructs a 2-read n-write multi-port memory unit by assembling 2R1W memories in parallel, allowing data to be written and read efficiently across multiple ports using a combination of spatial and time division techniques, including XOR operations, to minimize resource usage and enhance scalability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of memory ports is increased to support more slices (e.g., from 4 to 8), then the processing capacity and bandwidth are improved, but the area overhead and power consumption increase significantly
Solution Approach 1:
The memory system is divided into multiple banks, where each bank is a independent 2R1W memory unit. This segmentation allows the system to support multiple write ports by distributing write operations across different banks, thereby increasing processing capacity without proportionally increasing the area overhead of a single memory unit.
Solution Approach 2:
The patent transitions from a single-port memory architecture to a multi-port architecture by adding the bank dimension. Instead of increasing the port count of a single memory unit, the system uses multiple banks arranged in a dimensional structure, allowing multiple simultaneous write operations while maintaining reasonable area overhead per unit.
2Productivity
If the number of memory ports is increased to support more slices, then the processing capacity is improved, but the power consumption increases significantly
Solution Approach 1:
The memory system is divided into multiple banks, where each bank is an independent 2R1W memory unit. This segmentation allows the system to support multiple write ports by distributing write operations across different banks, thereby increasing processing capacity without proportionally increasing the area overhead of a single memory unit.
Solution Approach 2:
The patent transitions from a single-port memory architecture to a multi-port architecture by adding the bank dimension. Instead of increasing the port count of a single memory unit, the system uses multiple banks arranged in a dimensional structure, allowing multiple simultaneous write operations while maintaining reasonable area overhead per unit.
3Adaptability or versatility
If customized design methods are used to increase SRAM ports, then the port functionality is improved, but the design cycle and complexity increase
Solution Approach 1:
The patent merges multiple 2R1W memory units into a bank structure that collectively provides multi-port functionality. By combining simple 2R1W units with control logic, the system achieves n-write capability without requiring complex customized memory designs, thereby reducing design complexity while maintaining adaptability.
Solution Approach 2:
The 2R1W memory unit serves as a universal building block that can be replicated and configured to create memory systems with different numbers of write ports. This multi-functional approach allows the same basic unit to support various port configurations, reducing design complexity compared to creating customized memory designs for each port requirement.
4Adaptability or versatility
If algorithm design is used to construct multi-port memory, then the design flexibility is improved, but the resource overhead and processing time increase
Solution Approach 1:
The patent merges multiple 2R1W memory units into a bank structure that collectively provides multi-port functionality. By combining simple 2R1W units with control logic, the system achieves n-write capability without requiring complex customized memory designs, thereby reducing design complexity while maintaining adaptability.
Solution Approach 2:
The 2R1W memory unit serves as a universal building block that can be replicated and configured to create memory systems with different numbers of write ports. This multi-functional approach allows the same basic unit to support various port configurations, reducing design complexity compared to creating customized memory designs for each port requirement.
Data Source
AI summary
The present invention discloses a data processing method and system for a scalable multi-port memory. The multi-port memory is a 2-read n-write multi-port memory unit. The method comprises: assembling two 2R1W memories into one Bank memory unit; assembling n/2 Bank memory units in depth into a hardware architecture of one 2-read n-write multi-port memory unit; under one clock cycle, when data is written into the 2-read n-write multi-port memory unit, if the size of the data is less than or equal to the bit width of the 2R1W memory, writing the data into different 2R1W memories respectively; and if the size of the data is greater than the bit width of the 2R1W memory, waiting for a second clock cycle, and when the second clock cycle comes, writing the high and low bits of the written data into the two 2R1W memories of one Bank memory unit respectively.