Dual Boost Capacitor Write Driver Circuit for SRAM Leakage Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional memory technologies face challenges in reducing leakage of negative boost charge during the write assist period, leading to inefficient power usage and weakened bit line boosts, which affects the strength and density of SRAM bitcells.
Innovation Solution
The implementation of a dual boost capacitor system that provides a negative bit line boost to write driver inverters, where one boost capacitor enhances the gate voltage of NMOS transistors and another prevents discharge into the power supply, ensuring the NMOS transistors remain firmly off during the write assist period, thereby minimizing charge leakage and maintaining the negative boost strength.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a single boost capacitor is used to provide negative bit line boost during write assist period, then the access transistor strength is improved, but boost charge leaks to ground through the write driver, reducing efficiency
Solution Approach 1:
The patent divides the boost capacitor system into two separate capacitors: a first boost capacitor connected to the bit line and a second boost capacitor connected to the write driver input node. This segmentation prevents the write driver from discharging the boost charge to ground, as the second capacitor isolates the driver's ground path from the boost charge storage. The segmentation resolves the contradiction by maintaining access transistor strength through the first capacitor while eliminating energy loss through the second capacitor's isolation mechanism.
2Strength
If access transistors are made larger to strengthen them during write operations, then the write strength is improved, but the SRAM density is reduced
Solution Approach 1:
The patent changes the voltage parameter by applying a negative boost voltage to the bit line during write operations. This parameter change enhances the effective strength of the access transistor without physically enlarging it. The negative boost voltage modifies the transistor's operating conditions, allowing smaller transistors to achieve the same write strength that would otherwise require larger devices, thereby preserving SRAM density while maintaining write capability.
3Strength
If negative boost voltage is applied during write assist period, then the access transistor strength is enhanced, but the boost charge is discharged to ground through the write driver
Solution Approach 1:
The patent introduces a second boost capacitor as an intermediary element between the write driver and ground. This intermediary capacitor captures the boost charge that would otherwise be discharged to ground through the write driver. By placing this intermediary component in the circuit, the system maintains the negative boost voltage application for enhanced access transistor strength while preventing the discharge of boost charge, thus improving write operation efficiency through charge recovery.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces power consumption and enhances the negative bit line boost, maintaining the strength of the bit line discharge without wasting boost charge, thus improving the overall efficiency and density of SRAM bitcells.
Implementation Method 1
a first boost capacitor for providing a negative bit line boost that is applied to a first bit line during a write assist period
Implementation Method 2
a second boost capacitor for providing a negative boost to an input node for a write driver inverter
Data Source
AI summary
A pair of write driver inverters are arranged in series to drive a bit line responsive to a data bit input signal. A first boost capacitor provides a negative boost to a first ground node for a first one of the write driver inverters during the write assist period. A second boost capacitor provides a negative boost to a second ground node for a second one of the write driver inverters during the write assist period.