Multideck Memory Array Driver Architecture
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Solution Overview
Problem
Multideck memory array architectures face complexity in wiring arrangements due to the need for separate drivers for different groups of access lines, leading to inefficiencies and increased circuit complexity.
Innovation Solution
A conductive line architecture where access lines of adjacent levels are connected to a single driver, balancing the RC load and allowing for a unified driver configuration, reducing the number of driver types and simplifying circuit layout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate drivers are used for different groups of access lines in multideck memory arrays, then each driver can be optimized for its specific group, but the wiring arrangement becomes complicated and device complexity increases
Solution Approach 1:
The patent merges multiple drivers into a single shared driver that serves all access lines across multiple decks. This is achieved by implementing a common wordline driver that drives wordlines in different decks through different paths, eliminating the need for separate drivers for each deck and thereby reducing wiring arrangement complexity while maintaining driver optimization benefits
Solution Approach 2:
The single driver is designed with multi-functionality to drive access lines in multiple decks simultaneously. The driver can switch between different wordlines in different decks through control signals, making it a universal driver that performs the function of multiple dedicated drivers while reducing overall device complexity
2Adaptability or versatility
If multiple driver types are used for different access line groups, then each driver can be tailored to specific load requirements, but circuit layout becomes more complex
Solution Approach 1:
A single universal driver circuit is designed that can adapt to drive different wordlines in different decks through control signals. This driver can switch between driving wordlines in first deck, second deck, or both simultaneously, providing the flexibility of multiple driver configurations while maintaining a single simplified circuit layout
Solution Approach 2:
The driver circuit incorporates dynamic switching capability through control signals that determine which wordlines are active. The driver can dynamically reconfigure its output to serve different wordlines in different decks based on operational requirements, providing adaptability without requiring multiple static driver circuits
3Ease of operation
If access lines in adjacent levels are connected to different drivers, then each driver can independently control its lines, but signal dispersion increases and performance decreases
Solution Approach 1:
The patent combines multiple driver outputs into a single shared driver that controls access lines in adjacent levels. This unified driver approach reduces signal dispersion by providing a common signal source for all wordlines, improving signal integrity and access speed while maintaining the ability to independently select which wordlines are active through control signals
Data Source
AI summary
An array of memory cells in a multideck configuration comprising a plurality of superimposed decks, a plurality of access lines comprising at least a first plurality of access lines arranged in a first level, a second plurality of access lines arranged in a second level, and a third plurality of access lines arranged in a third level between the first plurality of access lines and the second plurality of access lines, the third plurality of access lines being arranged between two decks of the plurality of decks, a plurality of drivers configured to drive signals to the access lines, and connection elements configured to electrically connect the access lines to the respective drivers. The connections elements and the access lines are arranged so that a single driver of the plurality of drivers is configured to drive at least one access line of each level of the at least three levels.