Line Defect Detection Circuit for Semiconductor Memory Column Selection Lines
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Solution Overview
Problem
Semiconductor memory devices face yield loss and quality deterioration due to defects in column selection lines, which are not effectively detected during the wafer test process, leading to operational failures and improper screening of memory devices.
Innovation Solution
A line defect detection circuit is integrated into the semiconductor memory device, comprising a column decoder, line driver, initialization unit, latch driving unit, detection unit, and output control unit, to detect defects in column selection lines during the test operation and output a defect detection signal, enabling timely identification and discard of defective devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a line defect detection circuit is integrated into the semiconductor memory device, then detection capability and device quality are improved, but device complexity increases
Solution Approach 1:
The line defect detection circuit is integrated into the existing semiconductor memory device structure, merging the detection function with the memory device. The column decoder serves dual purposes: decoding column addresses during normal operation and applying test signals during test operations. The line defect detection circuit shares the column selection lines with the memory operation, eliminating the need for separate dedicated test equipment and reducing overall system complexity.
Solution Approach 2:
The column decoder is designed to perform multiple functions: it decodes column addresses during normal memory operations and applies test signals during defect detection operations. The column selection lines serve both memory access functions and defect detection functions. This multi-functionality reduces the need for additional dedicated components, thereby improving reliability without proportionally increasing device complexity.
2Measurement precision
If multiple column decoders are distributed across multiple banks, then detection coverage is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The semiconductor memory device is divided into multiple banks, with each bank having its own column decoder and line defect detection circuit. This segmentation allows independent testing of each bank's column selection lines, ensuring comprehensive defect detection coverage. Each bank can be tested independently, and the modular structure facilitates easier manufacturing and assembly compared to a monolithic design.
Solution Approach 2:
Column decoders are positioned in multiple spatial locations across different banks and at different column positions within each bank. This multi-dimensional distribution ensures that column selection lines are tested from various points in the device structure, improving detection coverage for defects that may occur at different locations in the column selection line network.
Data Source
AI summary
The semiconductor memory device includes a cell array unit comprising a plurality of cell mats; a column decoder suitable for outputting a plurality of column selection signals based on a column address to a plurality of column selection lines, respectively, during a normal operation, and for applying a signal having a first logic level to the plurality of column selection lines during a test operation; and a line defect detection circuit suitable for detecting whether a defect is present in the plurality of column selection lines in response to signals of the plurality of column selection lines, and outputting a defect detection signal based on the detection result, during the test operation.