SRAM Data-Controlled Power Supply for Write Margin
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Solution Overview
Problem
Conventional SRAM cells face issues with data read stability and write speed due to the Read-Select-Disturb and Half-Select-Disturb phenomena, exacerbated by lower supply voltage and increased threshold voltage variation in advanced manufacturing processes, which affect the stability and speed of data storage.
Innovation Solution
A SRAM with a data-controlled power supply that includes a Write-assist circuit dynamically adjusting power supply to memory cell circuits based on input data, using a cross-point double-layer pass-gate structure and requiring only 2 power-switch PMOSFETs and 2 power keepers per column, allowing for improved Write-ability and Write Margin without increasing bit-line loading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the access switch devices are sized down to reduce Read-Select-Disturb and Half-Select-Disturb, then data stability is improved, but write speed and Write Margin deteriorate
Solution Approach 1:
The power supply is segmented into two independent rails: a first power supply for the access switch devices and a second power supply for the latch circuit. This segmentation allows independent optimization of each component's operating conditions, enabling the access switch devices to be sized down for stability while maintaining adequate write performance through separate power control.
Solution Approach 2:
The invention changes the power supply parameter by introducing a second power supply rail with different voltage characteristics. By adjusting the power supply voltage independently for the latch circuit, the system can compensate for the reduced drive strength from smaller access switch devices, thereby maintaining write speed and Write Margin while achieving better data stability.
2Productivity
If the access switch devices are sized up to improve Write Margin and write speed, then write performance is improved, but Read-Select-Disturb and Half-Select-Disturb worsen
Solution Approach 1:
By segmenting the power supply into separate rails for access switch devices and latch circuit, the invention isolates the harmful disturb effects. The access switch devices can be sized up to improve write performance, while the latch circuit receives controlled power to minimize the impact of disturb phenomena on data stability.
Solution Approach 2:
The invention applies parameter changes by adjusting the power supply voltage to the latch circuit independently. This allows the system to tolerate larger access switch devices that cause disturb phenomena, as the latch circuit's power can be optimized to maintain stability despite the increased disturb effects from larger switch devices.
3Device complexity
If conventional power supply is used without data control, then circuit complexity is reduced, but write performance and power efficiency deteriorate
Solution Approach 1:
The invention introduces dynamic power supply control where the second power supply to the latch circuit is adjusted based on the data value being written. This dynamic adaptation enables the circuit to optimize its operating conditions for each write operation, improving write performance and power efficiency without requiring a fundamentally complex circuit architecture.
Solution Approach 2:
The invention changes the power supply parameter dynamically based on data values. By adjusting the voltage level of the second power supply according to the data being written, the system achieves better write performance and power efficiency while maintaining a relatively simple circuit structure that builds on conventional SRAM design.
4Loss of energy
If power supply voltage is lowered for low-power operation, then power consumption is reduced, but threshold voltage variation and stability worsen
Solution Approach 1:
The invention applies parameter changes by introducing a second power supply rail that can be independently adjusted. This allows the system to operate at lower overall power consumption while maintaining data stability through optimized power delivery to critical circuit components, effectively decoupling the relationship between supply voltage and threshold voltage variation.
Solution Approach 2:
The invention implements local quality by providing different power supply characteristics to different parts of the circuit. The latch circuit receives optimized power from the second supply to maintain stability, while the overall system operates at low power consumption, achieving local optimization of reliability without sacrificing global power efficiency.
Data Source
AI summary
A static random access memory with data controlled power supply, which comprises a memory cell circuit and at least one Write-assist circuit, for providing power to the memory cell circuit according to data to be written to the memory cell circuit.