Semiconductor Memory Clock Synchronization Circuit Power Down Recovery

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Solution Overview

Problem

Semiconductor memory devices face issues with clock skew and unstable internal clock timing due to power voltage drops when transitioning out of the power down mode, leading to non-predetermined timing of reference signals like DQS, which complicates satisfying the tDQSCK specification.

Innovation Solution

Incorporating an additional power voltage providing unit that supplies a second power voltage to the clock synchronization circuit, specifically the DLL or PLL, for a predetermined period after leaving the power down mode to maintain stable operation and prevent voltage drops, ensuring consistent delay values and timely internal clock generation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If power down mode is used to minimize current consumption, then power consumption is reduced, but voltage drops occur when transitioning out of power down mode causing unstable internal clock timing

Engineering Contradiction:

Improvepower consumptionVSAvoidinternal clock timing stability

Core Design Contradiction:

Use of energy by moving objectVSReliability

Solution Approach 1:

The patent applies preliminary action by providing an additional power voltage to the DLL circuit before the normal power voltage is fully restored after exiting power down mode. This prevents voltage drops that would cause unstable internal clock timing, ensuring the DLL operates reliably during the critical transition period when power voltages are changing.

Inventive Principle:

Principle #10Preliminary action

2Reliability

If additional power voltage is provided to DLL after power down mode, then internal clock timing stability is improved, but device complexity increases

Engineering Contradiction:

Improveinternal clock timing stabilityVSAvoidpower voltage providing circuit complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements universality by designing the additional power voltage providing unit to serve multiple functions: it provides power to the DLL circuit during power down mode transitions, works cooperatively with the normal power voltage, and can be integrated into existing power management structures. This multi-functional approach minimizes additional circuit complexity while achieving reliable clock timing.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Loss of time

If power voltage is immediately restored after power down mode, then response time is reduced, but voltage drops cause clock skew and timing issues

Engineering Contradiction:

Improvepower up response timeVSAvoidclock timing precision

Core Design Contradiction:

Loss of timeVSManufacturing precision

Solution Approach 1:

The patent applies beforehand cushioning by providing an additional power voltage that acts as a buffer during the power up transition from power down mode. This cushioning power voltage prevents the voltage drops that would otherwise cause clock skew and timing precision issues, while allowing the power voltage to be restored quickly without compromising timing accuracy.

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS8331190B2Semiconductor memory device and operation method thereof

Publication Date: 2012.12.11 SK HYNIX INC

AI summary

A semiconductor memory device includes a clock synchronizing unit for receiving a first power voltage through a first power voltage terminal, and an additional power voltage providing unit for additionally providing a second power voltage to the first power voltage terminal for a predetermined period after leaving a power down mode.