Semiconductor Memory Output Buffer Impedance Calibration
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Solution Overview
Problem
Conventional semiconductor devices face challenges in maintaining consistent impedance in output buffers due to variations in temperature and power source potential, which affects the high-speed output of read data, and this is compounded by limitations in pad layout flexibility due to the placement of calibration terminals.
Innovation Solution
A calibration circuit with replica output and replica pull-up/pull-down circuits is used to adjust transistor on/off states, ensuring impedance matches a prescribed value, and the placement of calibration terminals is optimized to improve pad layout flexibility without compromising calibration performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of transistors in pull-up and pull-down circuits is adjusted to maintain prescribed impedance, then impedance consistency is improved, but device complexity increases due to calibration operations
Solution Approach 1:
The patent uses replica circuits (copying the output buffer structure) to measure and calibrate impedance. The replica output buffer and replica pull-up/pull-down circuits create a simplified copy of the actual output buffer, allowing impedance measurement and calibration without directly affecting the main signal path. This copying approach enables automated calibration while maintaining impedance consistency.
Solution Approach 2:
The patent implements feedback through calibration circuits that measure the actual impedance of the output buffer and adjust the number of turned-on transistors accordingly. The calibration circuit compares the measured impedance with the target impedance value and provides feedback to control the transistor switching, ensuring impedance remains at the prescribed value despite temperature or voltage variations.
2Ease of manufacture
If calibration terminals are placed to optimize pad layout flexibility, then ease of manufacture is improved, but calibration performance may deteriorate
Solution Approach 1:
The patent resolves the pad layout conflict by utilizing different spatial dimensions and layers. The calibration terminals are placed in available pad locations that may be spatially separated from the data terminals, and the calibration circuit uses internal wiring and replica structures to establish the necessary measurement paths. This dimensional approach allows flexible pad arrangement while maintaining calibration accuracy through the replica circuit design.
3Device complexity
If transistor on resistance is used to provide impedance, then device complexity is reduced, but impedance stability deteriorates due to temperature and voltage variations
Solution Approach 1:
The patent applies dynamics by making the impedance characteristic adjustable rather than fixed. The calibration circuit dynamically controls the number of transistors turned on in the pull-up and pull-down circuits based on measured impedance values. This dynamic adjustment compensates for temperature and voltage variations, maintaining stable impedance despite environmental changes.
Solution Approach 2:
The patent changes the impedance parameter by adjusting the number of active transistors in the calibration process. Different numbers of transistors are turned on to achieve the target impedance value. This parameter change approach allows the system to adapt to varying conditions (temperature, voltage) by modifying the effective impedance through transistor switching configurations.
Data Source
AI summary
An apparatus includes a first terminal configured to communicate data with an outside of the apparatus, a second terminal configured to receive a first power source potential, a third terminal configured to receive a second power source potential lower than the first power source potential, a fourth terminal configured to be coupled to a calibration resistor, an output buffer including first to third nodes coupled to the first to third terminals respectively, and a replica circuit including fourth and fifth nodes coupled to the second and third terminals respectively, and sixth node coupled to the fourth terminal.