Configurable ECC Mode in DRAM for Memory Performance Scaling
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Solution Overview
Problem
Conventional methods face challenges in enhancing memory performance, particularly with DRAM, as frequency limits and channel scaling are restricted by conventional package technologies, making it difficult to improve memory performance alongside processor advancements.
Innovation Solution
The implementation of a configurable ECC mode in DRAM, which includes integrating ECC engines per bank group or across all banks, allowing for error correction and detection, and repurposing ECC bits as RAS bits for improved reliability and error handling during runtime.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional package technologies are used to couple processor to memory devices, then manufacturing and wiring implementation are simplified, but memory performance scaling is limited due to frequency limits and channel scaling restrictions
Solution Approach 1:
The patent transitions from conventional two-dimensional planar packaging to three-dimensional stacked architecture, where memory devices are stacked vertically above the processor die using through-silicon vias (TSVs). This vertical stacking enables multiple memory channels and increased bandwidth without increasing the horizontal footprint, thereby improving memory performance while managing package complexity through spatial reorganization.
Solution Approach 2:
The patent implements a nested structure where memory devices are stacked directly above the processor die, with intermediate packages and substrates providing structural support and electrical interconnection. The processor die is embedded within a multi-layer stack that includes memory devices, interposers, and packaging materials, creating a compact integrated memory system that improves performance while containing complexity within a unified package architecture.
2Productivity
If more memory channels are added to improve performance, then memory bandwidth increases, but channel scaling is limited by conventional package technologies
Solution Approach 1:
The patent utilizes the vertical dimension through 3D stacking to implement multiple independent memory channels. Each stack can contain multiple memory devices accessible through separate channel interfaces, allowing the system to scale bandwidth by adding vertical layers rather than horizontal channels. This approach overcomes the planar scaling limits of conventional packaging by exploiting the third dimension for channel multiplication.
3Speed
If frequency is increased to improve memory performance, then speed increases, but frequency limits are reached due to practical constraints in conventional package technologies
Solution Approach 1:
The patent embeds the processor and memory devices in a tightly integrated 3D stack with short interconnect paths through TSVs and minimal packaging material. This nested architecture reduces signal path length and parasitic inductance/capacitance compared to conventional external memory interfaces, enabling higher operating frequencies by minimizing the physical distance signals must travel between processor and memory.
4Reliability
If ECC engines are integrated per bank group or across all banks, then error correction capability and data integrity improve, but device complexity and resource usage increase
Solution Approach 1:
The patent implements a single configurable ECC engine that can operate in multiple modes: protecting individual bank groups or all banks collectively. This universal ECC engine provides versatile error correction coverage adaptable to different reliability requirements and performance scenarios, reducing the need for multiple dedicated ECC engines while maintaining flexible protection capabilities across the memory array.
Solution Approach 2:
The patent makes the ECC engine configuration dynamic and adaptable, allowing it to be programmed to protect different scopes (per bank group or all banks) based on system requirements. This dynamic configurability enables the ECC functionality to adjust its operation mode, coverage area, and resource allocation according to the specific reliability needs and performance demands of different workloads, optimizing the balance between error correction capability and device complexity.
Data Source
AI summary
Methods and apparatus for configurable ECC (error correction code) mode in DRAM. Selected memory cells in the bank arrays of a DRAM device (e.g., die) are used to store ECC bits. A DRAM device (e.g., die) is configured to operate in a first mode in which an on-die ECC engine employs selected bits in the arrays of memory cells in the DRAM banks as ECC bits to perform ECC operations and to operate in a second mode under which the ECC bits are not employed for ECC operations by the ECC engine and made available for external use by a host. In the second mode, the repurposed ECC bits may comprise RAS bits used for RAS (Reliability, Serviceability, and Availability) operations and/or metabits comprising metadata used for other operations by the host.