Configurable Logic Device Via Interconnects
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Solution Overview
Problem
The complexity and variety of digital logic ICs lead to high production costs and inventory management challenges, as well as delayed customer delivery due to the need for multiple specifications and large inventories, making it financially unfeasible to generate new logic families using traditional design methods.
Innovation Solution
A master design for a group of digital logic functions is implemented in early semiconductor processing steps, with late processing steps used to differentiate separate logic functions through upper metal level layer leads and vias, allowing for configuration of desired logic functions from a limited set of available functions, reducing the number of logic function parts and optimizing die area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If multiple logic families with different specifications are produced using traditional design methods, then customer delivery time increases and inventory costs increase, but manufacturing flexibility and product variety are maintained
Solution Approach 1:
The patent implements a universal logic device platform that can perform multiple logic functions through configurable interconnect structures. A single device design serves as a master template that can be configured to provide different logic families (TTL, CMOS, BiCMOS) and various logic functions (gates, flip-flops, multiplexers) without requiring separate dedicated designs for each variant.
Solution Approach 2:
The patent introduces dynamic configurability through programmable or selectable interconnect structures that allow the same physical device to change its logical function and electrical characteristics after manufacturing. This enables the device to adapt to different customer requirements for logic families and functions, reducing the need for multiple static designs and inventory variants.
2Speed
If a large inventory of multiple logic ICs is maintained to fill customer orders immediately, then customer delivery speed improves, but inventory holding costs increase significantly
Solution Approach 1:
By producing a limited inventory of universal configurable logic devices rather than multiple specialized logic family variants, the system can rapidly reconfigure existing inventory to meet different customer orders. This reduces inventory holding requirements while maintaining the ability to fulfill diverse customer demands promptly.
Solution Approach 2:
The patent prepares devices in an intermediate configurable state during manufacturing, where the basic logic structures are built but the final configuration is determined later based on customer orders. This preliminary preparation allows devices to be ready for rapid deployment to various applications without requiring pre-configured inventory for every possible variant.
3Reliability
If traditional one-part-at-a-time design methods are used for logic families, then each logic IC can be optimized for its specific function, but engineering design time and development costs increase
Solution Approach 1:
The patent merges multiple logic family designs and functions into a single unified device architecture. Instead of designing separate TTL, CMOS, and BiCMOS logic families independently over decades, the invention combines them into one master design that can be configured to provide any of these logic families and their associated functions, dramatically reducing engineering design time while maintaining optimization through configurable parameters.
Data Source
AI summary
An integrated circuit provides a semiconductor die with I/O bond pads, a power bond pad, and a circuit ground pad. Each I/O bond pad is associated with an input circuit that has an input circuit output lead. Sets of digital logic functional circuitry on the die provide different digital logic functions. Each function includes logic input leads and logic output leads. Output circuits each have an output circuit in lead and an output circuit out lead. Strapping structures, such as vias, formed in the semiconductor die electrically couple input circuits to a selected set of digital logic functions and the selected set of digital logic functions to output circuit in leads. Upper level metal conductors couple output circuit out leads and selected I/O bond pads.