Configurable Memory System with Dynamic Overlay Region Allocation
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Solution Overview
Problem
Conventional processor systems waste memory space and increase memory costs due to the use of large overlay regions in random-access memory, leading to slowed access speeds when storing unnecessary programs or processes.
Innovation Solution
A configurable memory system with an interface layer, overlay application layer, and memory relocatable layer, which allows for efficient relocation of memory addresses, reducing the need for multiple overlay regions and minimizing power and memory consumption by copying application processes from ROM to SRAM only when necessary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If large overlay regions of random-access memory are used for rapid data access, then access speed is improved, but memory space is wasted and memory cost increases
Solution Approach 1:
The patent divides the memory system into multiple overlay regions (first overlay region, second overlay region, etc.) that can be selectively activated. Instead of using one large overlay region for all applications, the system segments memory into smaller functional units that are allocated based on specific needs, thereby reducing overall memory space waste while maintaining rapid access speed for active regions.
Solution Approach 2:
The patent implements dynamic overlay region allocation where the system can switch between different overlay regions based on runtime requirements. The processor can dynamically select which overlay region to use for specific applications, allowing memory space to be adaptively managed without sacrificing access speed for the currently active region.
2Quantity of substance
If unnecessary programs or processes are stored in the overlay region of random-access memory, then memory space is utilized, but access speed slows down
Solution Approach 1:
The patent extracts only the necessary programs and processes into the active overlay region, leaving unnecessary content in other overlay regions or in different memory areas. By selectively copying only required application processes from ROM to the active overlay region in SRAM, the system optimizes access speed while still utilizing memory space efficiently through selective placement.
Solution Approach 2:
The patent applies different quality characteristics to different overlay regions, where the active overlay region is optimized for speed (containing only necessary programs), while other regions can store unnecessary or less frequently accessed content. This local differentiation allows each region to serve its specific purpose without compromising overall system performance.
3Adaptability or versatility
If multiple overlay regions are reserved in SRAM for flexibility, then programming design flexibility is improved, but power consumption and memory cost increase
Solution Approach 1:
The patent implements periodic switching between overlay regions based on application requirements. Instead of keeping multiple overlay regions actively reserved and powered simultaneously, the system activates only the required overlay region when needed, switches to ROM for other operations, and deactivates unused regions. This periodic activation pattern maintains programming flexibility while significantly reducing power consumption compared to continuous multi-region reservation.
Data Source
AI summary
The invention provides a configurable memory system including an interface layer, an overlay application layer, and a memory relocatable layer. The interface layer has a physical memory attribute module and a physical memory protection module. The interface layer manages memory attributes and memory security. The overlay application layer is coupled to the interface layer and executes an exception handler process to check if an overlay exception has occurred. The memory relocatable layer, coupled to the interface layer and the overlay application layer, having a plurality of resident service program within a first memory space, an overlay physical region within a second memory space, and a plurality of overlay virtual regions having application processes within a third memory space. The application processes of one of the overlay virtual regions is determined to be executed by the PMA module and is copied from the overlay virtual region to the overlay physical region by a processor.