Conformal Chip Edge Sealing for Hermetic IC Protection
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Solution Overview
Problem
Current hermetic sealing and crack protection methods for integrated circuit (IC) chips, such as metallic seal rings, consume significant chip area and can be damaged by high-stress dicing processes, leading to inefficiencies in chip production and potential failure due to moisture and contaminant exposure.
Innovation Solution
A conformal sealing layer with a higher coefficient of thermal expansion than silicon, applied to the chip edge sidewalls and top surface of the BEOL build-up structure, provides compressive stress and adhesion, potentially replacing traditional seal rings and improving chip area utilization by reducing the need for metallic sealing structures and minimizing damage from dicing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a metallic seal ring is used for hermetic sealing and crack protection, then the chip is protected from moisture and contaminants, but the chip area occupied by the seal ring increases
Solution Approach 1:
The patent replaces the traditional rigid metallic seal ring with a conformal sealing layer that forms a thin film over the chip edge sidewalls. This sealing layer is deposited conformally to follow the contours of the underlying structures, providing hermetic sealing with minimal area occupation. The thin film approach eliminates the need for a wide metallic ring while maintaining protection against moisture and contaminants.
Solution Approach 2:
The invention transitions from a planar metallic seal ring to a three-dimensional conformal sealing structure that coats the vertical sidewalls of the chip edge. By moving the sealing function into the vertical dimension and wrapping it around the chip perimeter, the solution achieves effective sealing without consuming horizontal chip area.
2Reliability
If a metallic seal ring is used for crack protection, then the chip is protected from crack propagation, but the seal ring may be damaged by high-stress dicing processes
Solution Approach 1:
The patent changes the material parameters of the sealing structure by using a conformal layer with different mechanical properties than metallic seal rings. The sealing layer is designed to be more compliant and less brittle, allowing it to withstand the high-stress dicing process without cracking or detaching, while still providing crack propagation resistance through its continuous coverage over the chip edge.
Solution Approach 2:
The conformal sealing layer is formed as a composite structure comprising multiple material layers with complementary properties. This composite construction provides both crack protection and resistance to dicing damage by combining materials that offer mechanical strength, adhesion, and flexibility, eliminating the vulnerability of single-material metallic seal rings to dicing stress.
3Area of stationary object
If a conformal sealing layer is used instead of a metallic seal ring, then chip area utilization is improved, but the sealing layer must provide equivalent hermetic sealing and crack protection
Solution Approach 1:
The conformal sealing layer is deposited as a thin film that conformally coats the chip edge sidewalls and underlying structures. This thin film provides hermetic sealing by creating a continuous, impermeable barrier that follows the exact contours of the underlying topography, ensuring equivalent sealing performance to metallic rings while occupying minimal area.
Solution Approach 2:
The conformal sealing layer is designed to perform multiple functions simultaneously: hermetic sealing, crack protection, and stress management. By integrating these functions into a single multi-layered structure, the invention achieves equivalent or superior reliability compared to traditional metallic seal rings while improving chip area utilization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The conformal sealing layer enhances chip protection against moisture, contaminants, and mechanical stress, increasing chip yield and wafer utilization by reducing the area occupied by traditional seal rings and allowing for more efficient dicing techniques, such as programmable dicing, which can handle fragile materials and irregularly shaped dies.
Implementation Method 1
The conformal sealing layer may be characterized by a higher coefficient of thermal expansion (CTE) than silicon
Data Source
AI summary
Chip sealing structures and methods of manufacture are described. In an embodiment, a chip structure includes a main body area formed of a substrate, a back-end-of-the-line (BEOL) build-up structure spanning over the substrate, and chip edge sidewalls extending from a back surface of the substrate to a top surface of the BEOL build-up structure and laterally surrounding the substrate and the BEOL build-up structure. In accordance with embodiments, the chip structure may further include a conformal sealing layer covering at least a first chip edge sidewall of the chip edge sidewalls and a portion of the top surface of the BEOL build-up structure, and forming a lip around the top surface of the BEOL build-up structure.