Congestion-Aware Interconnect Layer Promotion in IC Routing
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Solution Overview
Problem
Current routing and layer promotion methodologies in integrated circuit design fail to effectively address timing issues due to congestion and placement-based deficiencies, as they do not consider the potential mitigation of placement changes, leading to inefficient use of layer promotion as a resource.
Innovation Solution
A system that identifies candidate interconnects for layer promotion, scores and sorts them based on timing and placement factors, assesses routing demand and resource availability, and manages layer promotion iteratively to prioritize and prune interconnects, ensuring efficient use of resources and mitigating congestion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If layer promotion is applied to improve timing of interconnects, then timing constraints are met, but routing congestion increases
Solution Approach 1:
The patent applies local quality by differentiating the treatment of interconnects based on their specific characteristics. Candidate interconnects are identified and scored individually based on their timing deficiency and placement factors, rather than applying layer promotion uniformly. This allows timing-critical interconnects to be promoted while leaving non-critical ones on lower layers, thus improving timing without causing unnecessary congestion.
Solution Approach 2:
The patent changes the parameter of layer assignment from a static decision to a dynamic, iterative process. By scoring and ranking candidate interconnects based on timing and placement factors, the system selectively promotes interconnects to higher layers based on their specific needs, rather than changing all interconnects uniformly. This parameter-based selection resolves the contradiction by applying layer promotion only where necessary.
2Speed
If layer promotion is used to speed up interconnects, then signal transmission speed increases, but resource availability decreases
Solution Approach 1:
The patent applies partial action by selectively promoting only those interconnects that meet specific timing criteria and have high scores based on the scoring function. Rather than promoting all interconnects or using layer promotion excessively, the system identifies a subset of candidate interconnects and promotes them based on their timing deficiency and placement factors, thus using resources efficiently.
Solution Approach 2:
The patent introduces a scoring mechanism that evaluates interconnects based on multiple parameters including timing deficiency and placement factors. This parameter-based evaluation allows the system to prioritize which interconnects deserve layer promotion, optimizing the use of available layer resources while achieving the necessary speed improvements for critical paths.
3Productivity
If iterative layer promotion management is implemented to assess routing demand, then routing efficiency improves, but computational complexity increases
Solution Approach 1:
The patent applies preliminary action by performing scoring and ranking of candidate interconnects before actual layer promotion decisions are made. The scoring function evaluates timing and placement factors in advance, creating a prioritized list of candidates. This preliminary assessment simplifies the iterative process by pre-identifying which interconnects are most likely to benefit from layer promotion, reducing the computational burden during iteration.
Solution Approach 2:
The patent implements feedback through its iterative process where routing demand and resource availability are reassessed in each iteration based on previous promotion decisions. The scoring and ranking mechanism provides feedback on which interconnects should be promoted, and the iterative reassessment adjusts to the changing routing landscape, improving routing efficiency while managing computational complexity through structured feedback loops.
Data Source
AI summary
Embodiments relate to managing layer promotion of interconnects in the routing phase of integrated circuit design. An aspect includes a system to manage layer promotion in a routing phase of integrated circuit design. The system includes a memory device to store instructions, and a processor to execute the instructions to identify a set of candidate interconnects for layer promotion, score and sort the set of candidate interconnects according to a respective score to thereby establish a respective rank, assess routing demand and resource availability based on layer promotion of the set of candidate interconnects, and manage the set of candidate interconnects based on the respective rank and the resource availability, the processor assessing the routing demand and resource availability and managing the set of candidate interconnects iteratively, wherein the processor, in at least one iteration, generates a second set of candidate interconnects by reducing the set of candidate interconnects.