Contact Etch Stop Layer Stress Engineering for Transistor Performance
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Solution Overview
Problem
The continuous shrinkage of transistor dimensions in CMOS technology poses challenges in reliably creating critical circuit elements and maintaining performance, particularly due to increased complexity and production costs associated with stress-engineering techniques for strain-inducing layers in complex integrated circuits.
Innovation Solution
A technique that modifies the intrinsic stress of contact etch stop layers to reduce strain gradients between N-channel and P-channel transistors, using different stress values in less sensitive device regions and relaxed layers in sensitive areas to enhance transistor performance while minimizing production yield loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If strain-inducing layers are introduced to enhance transistor performance, then charge carrier mobility increases, but process complexity and production costs increase significantly
Solution Approach 1:
The patent changes the material composition parameter of the contact etch stop layer by incorporating silicon germanium (SiGe) with varying germanium concentrations (10-50%). This material parameter change enables intrinsic stress generation without requiring separate strain-inducing layers, thereby enhancing transistor performance while avoiding the complexity of additional process steps
Solution Approach 2:
The contact etch stop layer is given multiple functions: it serves as both an etch stop layer for contact hole formation and as a strain-inducing layer for enhancing transistor performance. By making the contact etch stop layer universal, the patent eliminates the need for separate strain-inducing layers, reducing process complexity while maintaining performance enhancement
2Reliability
If different stress characteristics are applied to N-channel and P-channel transistors to optimize individual performance, then transistor conductivity increases, but stress gradients cause defects and yield loss in high-density memory areas
Solution Approach 1:
The patent applies different germanium concentrations at different locations within the contact etch stop layer. Specifically, regions underlying N-channel transistors have different SiGe composition than regions underlying P-channel transistors, creating location-specific stress characteristics that optimize each transistor type's performance without causing harmful stress gradients in high-density memory areas
3Speed
If channel length is reduced to increase operating speed, then transistor switching speed increases, but manufacturing precision and reliability of critical dimensions decrease
Solution Approach 1:
The patent uses a deposited silicon germanium layer that can be selectively removed after serving its purpose of enhancing transistor performance during manufacturing. This disposable approach allows for performance enhancement without permanent structural modifications that would complicate subsequent processing of reduced-channel-length transistors
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces failure probability in complex integrated circuits by optimizing transistor performance in less sensitive regions while minimizing stress-induced issues in high-density memory areas, allowing for further device scaling without significant yield loss.
Implementation Method 1
forming a first dielectric layer having a first intrinsic mechanical stress over a first substrate region and a second substrate region
Implementation Method 2
modifying the first intrinsic mechanical stress in the second P-channel transistor and/or the second N-channel transistor
Data Source
AI summary
The present invention provides a technique for reducing stress or stress gradients in highly sensitive device regions, such as cache areas, while still providing high transistor performance in logic areas by correspondingly providing contact etch stop layers with compressive and tensile stress for P-channel transistors and N-channel transistors in these logic areas. Consequently, a reduced failure rate may be obtained.