Source/Drain Contact Liner Film for Stable Multi-Gate Scaling

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Solution Overview

Problem

Current semiconductor devices face challenges in scaling and reliability due to short channel effects and capacitance issues, particularly in multi-gate transistors, which require robust contact structures to maintain electrical stability and integration density.

Innovation Solution

A semiconductor device design featuring a substrate with active patterns, gate electrodes, spacers, source/drain patterns, and insulating films, including a liner film made of oxide-based materials, to enhance contact formation and reduce capacitance, thereby improving reliability and scalability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If pitch size is decreased to increase integration density, then integration density is improved, but capacitance between contacts increases and electrical stability deteriorates

Engineering Contradiction:
Improveintegration densityVSAvoidelectrical stability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

A liner film is introduced as an intermediary layer between the contact and the source/drain pattern. This liner film, made of oxide-based insulating material, acts as a mediator that reduces parasitic capacitance between the contact and the source/drain pattern, thereby maintaining electrical stability even when pitch size is decreased for higher integration density.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The invention changes the material parameter of the interface between contact and source/drain pattern by introducing an oxide-based insulating material as the liner film. This material parameter change reduces the capacitance value at the contact interface, allowing pitch size reduction without compromising electrical stability.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If multi-gate transistor structure is used to enhance current control, then current control capability is improved, but short channel effects become more significant requiring robust contact structures

Engineering Contradiction:
Improvecurrent control capabilityVSAvoidshort channel effects
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The liner film serves as an intermediary that mitigates the harmful effects of short channel effects by reducing parasitic capacitance at the contact interface. This allows multi-gate transistor structures to maintain effective current control without being overly affected by short channel effects, even at scaled dimensions.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Ease of manufacture

If contact structure is simplified for ease of manufacture, then manufacturing complexity is reduced, but electrical stability and reliability deteriorate

Engineering Contradiction:
Improvecontact structure fabricationVSAvoidelectrical stability
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The liner film is formed using standard semiconductor fabrication processes (such as atomic layer deposition) that are readily integrated into existing manufacturing flows. Despite adding a layer, the overall process complexity remains manageable while significantly improving electrical stability through capacitance reduction.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20240194752A1Semiconductor device
Publication Date: 2024.06.13 SAMSUNG ELECTRONICS CO LTD
  • US20240194752A1 patent drawing
  • US20240194752A1 patent drawing
  • US20240194752A1 patent drawing

AI summary

A semiconductor device includes a substrate, an active pattern disposed on the substrate and extending in a first direction, gate electrodes covering the active pattern and extending in a second direction, a gate spacer disposed on a sidewall of each of the gate electrodes, a source/drain pattern disposed between adjacent ones of the gate electrodes, an etch stop film disposed along a sidewall of the gate spacer and a profile of the source/drain pattern, an interlayer insulating film disposed between the adjacent ones of the gate electrodes with a contact trench exposing the source/drain pattern defined therein, a liner film disposed on an outer sidewall of the contact trench, and a source/drain contact disposed on the liner film and filling the contact trench, in which the source/drain contact is connected to the source/drain pattern. At least a portion of the liner film may be disposed in the source/drain pattern.