Contact Pad Spacer for Semiconductor Alignment Margin
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Solution Overview
Problem
As semiconductor devices integrate, the increasing aspect ratio of contact holes and thickness of interlayer insulating films narrow the alignment margin between buried contacts and contact pads, leading to a higher likelihood of device failure due to shorting.
Innovation Solution
A semiconductor device and fabrication method that reduce electrical defects by ensuring a sufficient margin between storage node contacts and bit line contact pads through the use of a contact pad spacer, where the cross-sectional area of the contact pad upper portion is equal to or less than the area at the interface with the spacer, and the side surface is perpendicular to the substrate, or has a trapezoidal shape, with nitride films used for spacers and insulating layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If the aspect ratio of contact holes increases due to integration enhancement, then the thickness of interlayer insulating film increases, but the alignment margin between contact holes decreases
Solution Approach 1:
The contact pad structure is divided into multiple portions: a first portion formed in the interlayer insulating film and a second portion formed in the contact pad spacer. This segmentation allows independent optimization of each portion's dimensions and positioning, enabling the upper contact pad area to be reduced while maintaining proper alignment with the bit line contact hole below, thus resolving the alignment margin issue caused by increased aspect ratio
Solution Approach 2:
The contact pad spacer acts as an intermediary structure between the interlayer insulating film and the upper contact pad. By forming the second portion of the contact pad within this spacer, the invention creates a transitional zone that facilitates precise alignment control. The spacer's presence allows the contact pad to be positioned accurately relative to the bit line contact hole, compensating for the reduced alignment margin caused by higher aspect ratios
2Duration of action of stationary object
If the aspect ratio of contact holes increases, then the alignment margin between buried contact and contact pad narrows, but the likelihood of device failure due to shorting increases
Solution Approach 1:
Dividing the contact pad into first and second portions enables independent dimensional control. The first portion in the interlayer insulating film can be sized to ensure adequate spacing from the buried contact, while the second portion in the spacer can be optimized for alignment with the bit line contact hole. This segmentation prevents shorting by maintaining proper electrical isolation between adjacent structures
Solution Approach 2:
The invention applies different dimensional characteristics to different portions of the contact pad. The first portion has dimensions optimized for preventing shorting with the buried contact, while the second portion has dimensions optimized for alignment with the bit line contact hole. This local differentiation of properties allows simultaneous achievement of both reliability goals
Data Source
AI summary
A semiconductor device and method of fabricating the same reduce the likelihood of the occurrence of electrical defects. The device includes a first interlayer insulating film on a semiconductor substrate; a contact pad spacer on the first interlayer insulating film; and a contact pad in the first interlayer insulating film and the contact pad spacer. The cross-sectional area of an upper portion of the contact pad in the contact pad spacer in a direction horizontal to the substrate is equal to or less than a cross-sectional area of an intermediate portion at an interface between the contact pad spacer and the first interlayer insulating film in a direction horizontal to the substrate.