Conductive Contact Segmentation for Parasitic Reduction in FinFET Devices
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Solution Overview
Problem
Parasitic resistance and capacitance in semiconductor devices degrade performance, particularly with scaling, necessitating reduction for high-performance devices.
Innovation Solution
A method of forming semiconductor devices involves creating fin-shaped channels with a gate structure and source/drain, followed by forming a metallic layer on the source/drain and a conductive contact that vertically overlaps only a portion of the metallic layer to reduce parasitic resistance and capacitance, respectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conductive contact is formed to cover the entire metallic layer, then electrical connection is improved, but parasitic capacitance increases
Solution Approach 1:
The conductive contact is segmented to cover only a portion of the metallic layer rather than the entire surface. This partial coverage approach maintains sufficient electrical connection while reducing the overlapping area between the conductive contact and gate structure, thereby minimizing parasitic capacitance formation.
Solution Approach 2:
The conductive contact is strategically positioned to provide localized electrical connection where most needed, rather than uniform coverage. By concentrating the conductive contact material in specific regions, the patent achieves effective electrical connection while minimizing the overall contact area that would contribute to parasitic capacitance.
2Productivity
If device dimensions are scaled down, then integration density is improved, but parasitic resistance increases
Solution Approach 1:
The patent employs a composite structure consisting of multiple layers including the metallic layer and conductive contact material. This composite approach allows optimization of each layer's properties to reduce parasitic resistance while maintaining scaled dimensions, addressing the increased parasitic resistance issue that arises with device scaling.
Solution Approach 2:
The patent extends the metallic layer beyond the immediate contact region, creating a larger surface area in the planar dimension. This dimensional extension provides multiple parallel conduction paths, effectively reducing parasitic resistance without increasing the vertical device height, thus maintaining integration density.
Data Source
AI summary
Methods of forming a semiconductor device are provided. The methods may include forming a plurality of fin-shaped channels on a substrate, forming a gate structure crossing over the plurality of fin-shaped channels and forming a source/drain adjacent a side of the gate structure. The source/drain may cross over the plurality of fin-shaped channels and may be electrically connected to the plurality of fin-shaped channels. The methods may also include forming a metallic layer on an upper surface of the source/drain and forming a conductive contact on the metallic layer opposite the source/drain. The conductive contact may have a first length in a longitudinal direction of the metallic layer that is less than a second length of the metallic layer in the longitudinal direction of the metallic layer.