Continuous Gate Fin Spacer Layout for 10 nm Pitch Scaling
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Solution Overview
Problem
Current semiconductor fabrication processes face challenges in scaling to the 10 nanometer node or smaller due to variability in conventional methods, necessitating new methodologies or technologies to optimize performance and achieve tighter pitch and smaller feature sizes for advanced integrated circuit structures.
Innovation Solution
The implementation of pitch quartering and merged fin pitch quartering approaches in semiconductor fabrication, combined with advanced trench isolation and fin trim processes, to form semiconductor fins and integrate multi-gate transistors, allowing for tighter pitch and smaller feature sizes while maintaining transistor performance and density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used, then manufacturing simplicity is maintained, but manufacturing precision deteriorates at 10 nanometer node or smaller
Solution Approach 1:
The fabrication process is divided into multiple discrete stages: forming mandrels at a first pitch, depositing spacers, selectively removing mandrels and spacers to create fins at a quartered pitch. This segmentation enables precise control of feature dimensions at 10nm node by breaking the complex patterning into controllable steps, directly resolving the contradiction between manufacturing precision and process complexity.
Solution Approach 2:
Mandrels are formed in advance at a relaxed pitch that is achievable with conventional lithography. Spacers are deposited on these pre-formed mandrels before the final fin patterning. This preliminary action allows the use of less advanced lithography tools while achieving tighter final pitch, resolving the contradiction by preparing structures beforehand that enable subsequent precision work.
2Manufacturing precision
If pitch quartering is implemented, then manufacturing precision improves, but device complexity increases
Solution Approach 1:
The structure is built hierarchically with spacers nested on mandrels, and fins ultimately formed from the spacer patterns. Each layer serves as a template for the next, with the final fin pitch being one-quarter of the original mandrel pitch. This nested approach enables precise pitch quartering through systematic layering rather than attempting direct single-step patterning, managing the complexity through structured progression.
Solution Approach 2:
The process transitions from two-dimensional lithographic patterning to three-dimensional structure formation using vertical spacers and multi-layer stacking. By adding the vertical dimension with spacer deposition and selective removal, the method achieves pitch quartering that would be impossible with planar lithography alone, resolving the precision-complexity contradiction through dimensional expansion.
3Productivity
If feature size is reduced, then transistor density improves, but manufacturing precision becomes more difficult to maintain
Solution Approach 1:
Spacers are formed through conformal deposition processes that automatically create uniform thickness layers on the mandrel sidewalls. The spacer width is determined by deposition thickness rather than lithographic patterning, making the final fin pitch self-defined by the spacer geometry. This self-service mechanism inherently maintains manufacturing precision as feature sizes are reduced, since the critical dimensions are set by deposition control rather than lithography resolution.
Data Source
AI summary
Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An insulating structure is directly adjacent sidewalls of the lower fin portion of the fin. A first gate electrode is over the upper fin portion and over a first portion of the insulating structure. A second gate electrode is over the upper fin portion and over a second portion of the insulating structure. A first dielectric spacer is along a sidewall of the first gate electrode. A second dielectric spacer is along a sidewall of the second gate electrode, the second dielectric spacer continuous with the first dielectric spacer over a third portion of the insulating structure between the first gate electrode and the second gate electrode.