Control Switches for Reducing Pin Capacitance in Stacked Semiconductor Die

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Solution Overview

Problem

Conventional semiconductor devices with stacked die experience parasitic capacitance ('pin cap') due to non-enabled die pins, leading to increased power consumption and limited input/output (I/O) signal transfer speed, which worsens as the number of die in the stack increases.

Innovation Solution

The implementation of control switches, formed as micro-electromechanical (MEMS) devices on a substrate or integrated circuits, electrically isolates non-enabled semiconductor die in the stack, allowing only the enabled die to receive signals while keeping others in a standby mode, thereby reducing parasitic capacitance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If multiple semiconductor die are stacked to increase storage capacity, then storage capacity is improved, but parasitic capacitance increases leading to higher power consumption and limited I/O signal transfer speed

Engineering Contradiction:
Improvestorage capacityVSAvoidpower consumption
Core Design Contradiction:
Quantity of substanceVSUse of energy by moving object

Solution Approach 1:

The patent applies segmentation by dividing the die stack into multiple independently controllable groups, where each group can be enabled or disabled separately through control switches. This allows only the necessary portions of the die stack to remain active, reducing the total parasitic capacitance and power consumption while maintaining high storage capacity through the stacked architecture.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic control of die stack operation through control switches that can dynamically enable or disable specific die or groups of die based on operational requirements. This dynamic switching capability allows the system to adapt power consumption and signal routing to actual needs, preventing unnecessary power drain on inactive die while maintaining high storage capacity.

Inventive Principle:
Principle #15Dynamics

2Quantity of substance

If multiple semiconductor die are stacked to increase storage capacity, then storage capacity is improved, but parasitic capacitance increases leading to limited I/O signal transfer speed

Engineering Contradiction:
Improvestorage capacityVSAvoidI/O signal transfer speed
Core Design Contradiction:
Quantity of substanceVSSpeed

Solution Approach 1:

The patent segments the die stack into independently controllable groups with dedicated control switches, allowing signal routing to be confined to only the active die. This segmentation reduces the capacitive loading on I/O signals by excluding inactive die from the signal path, thereby improving signal transfer speed while preserving high storage capacity through the stacked configuration.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent extracts or removes the parasitic capacitance effect by using control switches to electrically isolate inactive die from the signal path. By taking out the harmful capacitive coupling to inactive die, the I/O signal transfer speed is improved while the stacked die architecture maintains high storage capacity.

Inventive Principle:
Principle #2Taking out (Extraction)

3Use of energy by moving object

If control switches are added to electrically isolate non-enabled die, then power consumption is reduced, but device complexity increases

Engineering Contradiction:
Improvepower consumptionVSAvoiddevice complexity
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The control switches are designed with multi-functionality, serving both as signal routing elements and as power management components. Each control switch simultaneously enables/disables signal transmission and controls power delivery to specific die, reducing the need for separate control circuits and thereby limiting the increase in device complexity while achieving significant power consumption reduction.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The control switches act as intermediary elements between the controller and the die stack, providing a compact interface that manages both signal routing and power distribution. This intermediary function consolidates control logic and reduces the overall system complexity compared to having separate control mechanisms for signal and power management.

Inventive Principle:
Principle #24Intermediary (Mediator)

4Speed

If control switches are added to electrically isolate non-enabled die, then I/O signal transfer speed is enhanced, but device complexity increases

Engineering Contradiction:
ImproveI/O signal transfer speedVSAvoiddevice complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The control switches perform multiple functions simultaneously: they route I/O signals to the correct die and provide electrical isolation to enhance signal integrity and speed. This multi-functionality reduces the need for additional dedicated signal isolation components, thereby enhancing I/O signal transfer speed while limiting the increase in device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The control switches serve as intermediary components that simplify the overall system architecture by consolidating signal routing and electrical isolation functions in a single element. This intermediary role reduces the number of separate components needed, thereby enhancing I/O signal transfer speed through improved signal integrity while minimizing the increase in device complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11177239B2Semiconductor device including control switches to reduce pin capacitance
Publication Date: 2021.11.16 SAMSUNG ELECTRONICS CO LTD
  • US11177239B2 patent drawing
  • US11177239B2 patent drawing
  • US11177239B2 patent drawing

AI summary

A semiconductor device including control switches enabling a semiconductor die in a stack of semiconductor die to send or receive a signal, while electrically isolating the remaining die in the die stack. Parasitic pin cap is reduced or avoided by electrically isolating the non-enabled semiconductor die in the die stack.