Conversion Power Logic for Memory Address Energy Optimization
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Solution Overview
Problem
Conventional computer processors consume excessive electrical power due to unnecessary address conversion processes in segmented memory schemes, which can be optimized for energy efficiency.
Innovation Solution
Incorporating conversion power logic within the processor to determine if effective addresses require conversion to linear addresses, and blocking such conversions when not necessary, thereby reducing power consumption by utilizing execution components and clock gating logic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If address conversion is performed for all memory access operations in segmented memory schemes, then memory addressing functionality is ensured, but electrical power consumption increases
Solution Approach 1:
The patent applies preliminary action by checking whether address conversion is necessary before performing the conversion operation. The conversion power logic evaluates conditions (such as determining if the current code segment base address is zero) to predict whether conversion will be needed, and only enables the conversion circuitry when necessary. This prevents unnecessary power consumption while ensuring memory addressing functionality is maintained when required.
2Use of energy by moving object
If address conversion operations are blocked to reduce power consumption, then electrical power efficiency improves, but memory access functionality may be compromised
Solution Approach 1:
The patent implements feedback through conversion power logic that continuously monitors system state (such as code segment base address values) and dynamically controls whether address conversion is performed. This feedback mechanism ensures that conversion is enabled only when the system state indicates it is necessary, thereby maintaining memory access functionality while optimizing power efficiency by blocking conversions when the feedback indicates they are unnecessary.
Data Source
AI summary
In an embodiment, a processor includes a plurality of cores. Each core includes conversion power logic to receive an instruction including an untranslated memory address, determine whether a code segment (CS) base address is equal to zero, and in response to a determination that the CS base address is equal to zero, execute the instruction using the untranslated memory address. Other embodiments are described and claimed.