Power Converter Capacitor Layout for Low-Inductance Noise Bypass
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Solution Overview
Problem
Existing electric power converters face challenges in downsizing while ensuring insulation resistance between lines and ground, particularly due to parasitic inductance issues with capacitors at higher frequencies, which affect noise bypass performance.
Innovation Solution
The implementation of capacitors arranged in specific configurations to minimize parasitic inductance, including series and parallel connections, and optimizing magnetic flux directions to reduce common mode noise, allowing the use of smaller capacitors with sufficient insulation resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a capacitor with larger size is adopted to ensure insulation resistance between line and ground, then insulation resistance is improved, but device size increases
Solution Approach 1:
The patent divides the single Y capacitor into multiple capacitors (first Y capacitor and second Y capacitor) connected in parallel between the neutral line and ground line. This segmentation allows each capacitor to handle a portion of the insulation requirement, enabling the use of smaller individual capacitors while collectively achieving the required insulation resistance.
Solution Approach 2:
The patent combines multiple capacitors in parallel configuration to achieve the desired insulation resistance. By merging the capacitance values of multiple smaller capacitors, the system attains the equivalent performance of a single larger capacitor without the associated size and parasitic inductance penalties.
2Productivity
If operating frequency is increased to improve efficiency and reduce size, then productivity is improved, but parasitic inductance effects worsen
Solution Approach 1:
The patent segments the capacitor network into multiple smaller capacitors arranged in specific configurations (series and parallel combinations). This segmentation reduces the parasitic inductance of each individual capacitor, and when combined, the overall parasitic inductance is lower than that of a single large capacitor, enabling effective operation at higher frequencies.
Solution Approach 2:
The patent changes the electrical parameters of the capacitor network by using multiple capacitors with optimized capacitance values and configurations. This parameter optimization minimizes the resonant frequency formed by parasitic inductance and capacitance, pushing it beyond the operating frequency range and thereby reducing the harmful effects of parasitic inductance at high frequencies.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables further downsizing of electric power converters while maintaining effective insulation resistance and improved noise filtering, particularly at higher frequencies.
Implementation Method 1
each of the X capacitor and the Y capacitor has a parasitic inductance caused by electrode structure or the like
Implementation Method 2
optimizing magnetic flux directions to reduce common mode noise
Data Source
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AI summary
An electric power converter is configured to perform conversion of power supplied from a power source. The electric power converter includes: a plurality of first capacitors connected in series between two lines to be used for supply of the power; and at least one second capacitor connected between a ground and a connection point between two first capacitors among the plurality of first capacitors.