Power Converter Loop Gain Adaptation for PWM-PFM Transitions
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Solution Overview
Problem
Switching power converters face inefficiencies and voltage ripple during mode transitions due to variations in control loop gain caused by inductor inductance, duty cycle ratio, and PWM switching frequency, leading to degraded load transient performance and mode bouncing.
Innovation Solution
Adapt the reference voltage level for the PFM timer based on inductor current ripple to maintain consistent control loop gain across modes, using a digital-to-analog converter to adjust the reference voltage and current levels for the PFM pulse.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the power converter operates in both PWM and PFM modes with fixed control loop gain, then the device complexity is reduced, but the output voltage ripple increases and load transient performance degrades during mode transitions
Solution Approach 1:
The patent implements dynamic control loop gain adaptation by adjusting the PFM timer reference voltage based on the operational mode (PWM or PFM). This allows the control loop gain to vary dynamically according to the operating conditions, optimizing performance in each mode while reducing output voltage ripple during transitions.
Solution Approach 2:
The patent changes the reference voltage parameter of the PFM timer to adapt the control loop gain. By modifying this voltage parameter based on the operational mode, the system achieves optimal control performance in both PWM and PFM modes without increasing overall device complexity.
2Measurement precision
If the PFM pulse size is adjusted to improve control loop gain, then the control precision is improved, but the inductance variations and duty cycle changes cause gain instability
Solution Approach 1:
The patent uses feedback from the operational mode detection to adjust the PFM timer reference voltage. This feedback mechanism ensures that the control loop gain remains stable and precise by compensating for variations caused by inductance changes and duty cycle adjustments.
Solution Approach 2:
The patent preemptively adjusts the reference voltage level before mode transitions occur by detecting the operational mode in advance. This preliminary adjustment of the PFM timer reference voltage ensures smooth transitions and maintains control loop gain stability without waiting for ripple issues to manifest.
Data Source
AI summary
Described embodiments include a circuit having a comparator with first and second comparator inputs and a comparator output. The second comparator input is coupled to a ripple reference voltage terminal. A switch is coupled between the first comparator input and a ground terminal, and has a switch control terminal that is coupled to the comparator output. A capacitor is coupled between the first comparator input and the ground terminal. A first current source is coupled between a supply terminal and the first comparator input, and has a first current control terminal. A second current source is coupled between a current output terminal and the ground terminal, and has a second current control terminal.