Converter With Partially Thinned Leadframe And Stacked Chips
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Solution Overview
Problem
Existing power switching devices for DC/DC converters face challenges in miniaturization, as they require significant board area and height due to the use of wires and clips, which introduce parasitic inductance and resistances, and the integration of driver-and-controller ICs adds complexity and real estate requirements.
Innovation Solution
A power supply system with a vertically stacked configuration using a QFN leadframe, a flat interposer, and integrated driver-and-controller circuitry on the high-side chip, eliminating the need for bonding wires and clips, and incorporating a partially thinned leadframe with a recessed pocket for the low-side chip and patterned interposer traces for efficient heat dissipation and reduced height.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bonding wires are used to connect chips to leads, then electrical connections are established, but parasitic inductance and resistance are introduced into the power circuit
Solution Approach 1:
The patent removes bonding wires from the power circuit path entirely. Instead, power connections are made through direct metallurgical bonds between chip pads and leadframe pads, and through the leadframe structure itself, extracting the harmful element (bonding wires) from the power signal path while maintaining necessary electrical connections
Solution Approach 2:
The leadframe serves as an intermediary structure that provides both mechanical support and low-inductance electrical pathways. The leadframe's metallurgical bonds and conductive structure mediate between the chips and external connections, replacing the high-inductance bonding wire paths with lower-inductance alternative pathways
2Object-generated harmful factors
If clips are used to substitute for bonding wires, then parasitic inductance is reduced, but device height and board area are increased
Solution Approach 1:
The patent transitions from a planar arrangement with vertical clips to a three-dimensional stacked configuration where chips are vertically positioned on the leadframe pad. This dimensional change allows power connections to be made through the vertical stack via metallurgical bonds, eliminating the need for lateral clip extensions and reducing overall device height
Solution Approach 2:
The patent merges the functions of mechanical support, electrical connection, and thermal management into the leadframe structure itself. The leadframe provides structural support, low-inductance power pathways through its metallurgical bonds, and thermal conduction to the PCB, consolidating multiple functions that were previously distributed across separate components
3Adaptability or versatility
If driver-and-controller IC is assembled horizontally side-by-side with FET chips, then all components are connected, but board real estate requirements are increased and assembly complexity is added
Solution Approach 1:
The patent stacks the driver-and-controller IC vertically on top of the low-side FET chip rather than arranging it horizontally beside the chips. This vertical stacking in the third dimension reduces the horizontal footprint on the PCB while maintaining all necessary electrical connections through vertical metallurgical bonds and leadframe pathways
4Power
If synchronous buck converter configuration is used with control FET and sync FET chips, then power conversion function is achieved, but significant parasitic inductance is introduced into the power circuit
Solution Approach 1:
The patent extracts bonding wires from the high-current power switch nodes, eliminating the primary source of parasitic inductance. Power connections are made through direct metallurgical bonds between chip pads and leadframe pads, and through the leadframe's low-inductance pathways to the PCB, removing the harmful inductive elements from the power circuit
Solution Approach 2:
The patent replaces the mechanical bonding wire system with a metallurgical bonding system. Instead of wrapping wires around pins and soldering them, the chips are directly bonded to the leadframe pads through metallurgical processes, creating rigid, low-inductance connections that are electrically and mechanically superior for high-frequency power switching applications
Data Source
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AI summary
In described examples, a power supply system (100) includes vertically sequentially a QFN leadframe (101), a first chip with FET terminals on opposite sides, a flat interposer (120), and a second chip (130) with FET terminals and the terminals of the integrated driver-and-control circuit on a single side. The leadframe (101) pad has a portion recessed as pocket with a depth and an outline suitable for attaching the first chip with one terminal in the pocket and the opposite terminal co-planar with the un-recessed pad surface. The interposer includes metal patterned in traces separated by gaps; the traces include metal of a first height and metal of a second height smaller than the first height, and insulating material filling the gaps and the height differences; one interposer side attached to the leadframe pad with the first chip, the opposite interposer side attached to the terminals of the second chip.