Convex-Bottom Cavities for Void-Resistant Interconnect Fill
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Solution Overview
Problem
The scaling down of semiconductor devices poses challenges in metal line gap fill due to increased aspect ratios of cavities such as vias and trenches, and the formation of barrier layers like TaN becomes difficult at scaled dimensions, particularly in dual damascene processing.
Innovation Solution
A method is employed to form cavities with a convex profile at the bottom surface, facilitating the formation of a continuous barrier layer along the sidewalls and bottoms of these cavities, followed by filling with conductive material to create conductive interconnects, using etching processes that etch the sidewalls faster than the central region, resulting in a convex bottom profile.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional etching processes are used to form cavities, then the cavity depth is uniform, but void formation occurs in conductive interconnects due to discontinuous barrier layers
Solution Approach 1:
The patent applies asymmetry by creating a non-uniform cavity profile where the bottom surface is elevated at the center relative to the periphery. This asymmetric convex profile ensures that barrier layer deposition occurs continuously across the cavity bottom, preventing void formation while maintaining manufacturing feasibility through controlled etching processes
Solution Approach 2:
The patent implements local quality by varying the cavity depth at different locations - shallower at the center and deeper at the periphery. This localized variation in cavity geometry ensures continuous barrier layer formation at the critical center region while maintaining adequate depth at the periphery for complete fill, thereby resolving the contradiction between barrier layer continuity and cavity uniformity
2Adaptability or versatility
If cavity aspect ratio is increased to accommodate scaled down dimensions, then device scaling is achieved, but barrier layer formation becomes increasingly difficult
Solution Approach 1:
The patent changes the geometric parameters of the cavity by introducing a convex profile with elevated central region. This parameter modification reduces the effective aspect ratio at the cavity center where barrier layer formation is most critical, making it easier to form continuous barrier layers even as overall device dimensions are scaled down
3Productivity
If spacing between vias and trenches is reduced, then device density is improved, but continuous barrier layer formation becomes more difficult
Solution Approach 1:
The patent applies local quality by creating a convex cavity profile that provides enhanced barrier layer formation capability at the central region between vias and trenches. This localized geometric modification ensures continuous barrier layer coverage even when spacing is reduced, thereby maintaining reliability while improving device density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces void formation in conductive interconnects by ensuring a continuous barrier layer is formed, enhancing the integrity and reliability of the conductive structures.
Implementation Method 1
An etching process is performed to etch the dielectric material to form a cavity
Implementation Method 2
depositing a barrier layer along the bottom of the cavity
Data Source
AI summary
Provided are conductive structures located within dielectric material, and methods for fabricating such structures and devices. An exemplary method includes providing a substrate having a conductive feature in a first dielectric layer; depositing a second dielectric layer over the conductive feature and the first dielectric layer; etching the second dielectric layer to form a cavity through the second dielectric layer, wherein the cavity has a bottom with a convex profile; depositing a barrier layer along the bottom of the cavity; and depositing a conductive material in the cavity to form a structure electrically connected to the conductive feature.


