Convex Gate Electrode Reducing Coupling Capacitance in Nonvolatile Memory
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Solution Overview
Problem
Current nonvolatile semiconductor memory devices face challenges in operational speed due to high coupling capacitance between gate electrodes, which affects charging time and drain current, leading to reduced performance.
Innovation Solution
The design includes a semiconductor memory device with a first gate electrode and a second gate electrode electrically insulated from the first, with an insulating film for charge trapping, and a convex shape for the first gate electrode, reducing coupling capacitance by increasing the distance between the upper portion of the first gate electrode and the second gate electrode, while maintaining a channel formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the distance between gate electrodes is reduced to increase storage density, then storage capacity is improved, but coupling capacitance increases leading to reduced operational speed
Solution Approach 1:
The first gate electrode is configured with a convex shape in cross-section, creating three-dimensional spatial separation. The upper portion of the first gate electrode is positioned farther from the second gate electrode compared to the lower portion, effectively utilizing vertical and lateral dimensions to reduce coupling capacitance while maintaining horizontal density
Solution Approach 2:
The first gate electrode employs an asymmetric convex cross-sectional shape rather than a symmetric rectangular structure. This asymmetric geometry creates varying distances between gate electrodes at different heights, reducing overall coupling capacitance while maintaining effective channel control
2Speed
If the distance between gate electrodes is increased to reduce coupling capacitance, then operational speed is improved, but storage density decreases
Solution Approach 1:
Different regions of the first gate electrode have different distances to the second gate electrode. The lower portion maintains close proximity for effective channel control, while the upper portion is positioned farther away to reduce coupling capacitance. This local variation in distance optimizes both speed and density
3Ease of manufacture
If the gate electrode structure is simplified for ease of manufacture, then manufacturing complexity is reduced, but coupling capacitance control capability is worsened
Solution Approach 1:
The first gate electrode is formed with a convex curved cross-sectional shape instead of sharp rectangular corners. This curvature can be achieved through standard semiconductor processing techniques such as rounded etching or deposition, maintaining manufacturing simplicity while providing superior coupling capacitance control compared to rectangular structures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves operational speed by reducing coupling capacitance and maintaining effective channel formation, thereby enhancing both speed and current properties of the memory device.
Implementation Method 1
an insulating film-formed at least between the semiconductor substrate and the second gate electrode to trap electric charge, as an electric charge trapping film
Data Source
AI summary
A nonvolatile semiconductor memory device includes: a semiconductor substrate; a first gate electrode formed on the semiconductor substrate through a gate insulating film; a second gate electrode formed in a side direction of the first gate electrode and electrically insulated from the first gate electrode; and an insulating film formed at least between the semiconductor substrate and the second gate electrode to trap electric charge, as an electric charge trapping film. The first gate electrode comprises a lower portion contacting the gate insulating film and an upper portion above the lower portion of the first gate electrode, and a distance between the upper portion of the first gate electrode and the second gate electrode is longer than a distance between the lower portion of the first gate electrode and the second gate electrode.